📄 bingxingru.rpt
字号:
- 2 - B 10 DFFE + 2 1 0 1 data7 (:38)
- 8 - B 10 DFFE + 2 1 0 1 data6 (:39)
- 7 - B 10 DFFE + 2 1 0 1 data5 (:40)
- 6 - B 10 DFFE + 2 1 0 1 data4 (:41)
- 5 - B 10 DFFE + 2 1 0 1 data3 (:42)
- 4 - B 10 DFFE + 2 1 0 1 data2 (:43)
- 3 - B 10 DFFE + 2 1 0 1 data1 (:44)
- 1 - B 10 DFFE + 2 0 0 1 data0 (:45)
- 4 - B 09 DFFE + 1 2 1 0 :50
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\zuixin\bingxingru.rpt
bingxingru
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 6/ 96( 6%) 1/ 48( 2%) 0/ 48( 0%) 5/16( 31%) 1/16( 6%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zuixin\bingxingru.rpt
bingxingru
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 9 clk
Device-Specific Information: f:\zuixin\bingxingru.rpt
bingxingru
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 9 rest
Device-Specific Information: f:\zuixin\bingxingru.rpt
bingxingru
** EQUATIONS **
clk : INPUT;
load : INPUT;
N0 : INPUT;
N1 : INPUT;
N2 : INPUT;
N3 : INPUT;
N4 : INPUT;
N5 : INPUT;
N6 : INPUT;
N7 : INPUT;
rest : INPUT;
-- Node name is ':45' = 'data0'
-- Equation name is 'data0', location is LC1_B10, type is buried.
data0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!rest), VCC, VCC);
_EQ001 = load & N0;
-- Node name is ':44' = 'data1'
-- Equation name is 'data1', location is LC3_B10, type is buried.
data1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!rest), VCC, VCC);
_EQ002 = data0 & !load
# load & N1;
-- Node name is ':43' = 'data2'
-- Equation name is 'data2', location is LC4_B10, type is buried.
data2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!rest), VCC, VCC);
_EQ003 = data1 & !load
# load & N2;
-- Node name is ':42' = 'data3'
-- Equation name is 'data3', location is LC5_B10, type is buried.
data3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!rest), VCC, VCC);
_EQ004 = data2 & !load
# load & N3;
-- Node name is ':41' = 'data4'
-- Equation name is 'data4', location is LC6_B10, type is buried.
data4 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!rest), VCC, VCC);
_EQ005 = data3 & !load
# load & N4;
-- Node name is ':40' = 'data5'
-- Equation name is 'data5', location is LC7_B10, type is buried.
data5 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!rest), VCC, VCC);
_EQ006 = data4 & !load
# load & N5;
-- Node name is ':39' = 'data6'
-- Equation name is 'data6', location is LC8_B10, type is buried.
data6 = DFFE( _EQ007, GLOBAL( clk), GLOBAL(!rest), VCC, VCC);
_EQ007 = data5 & !load
# load & N6;
-- Node name is ':38' = 'data7'
-- Equation name is 'data7', location is LC2_B10, type is buried.
data7 = DFFE( _EQ008, GLOBAL( clk), GLOBAL(!rest), VCC, VCC);
_EQ008 = data6 & !load
# load & N7;
-- Node name is 'dout'
-- Equation name is 'dout', type is output
dout = _LC4_B9;
-- Node name is 'rest~1'
-- Equation name is 'rest~1', location is LC1_B9, type is buried.
-- synthesized logic cell
!_LC1_B9 = _LC1_B9~NOT;
_LC1_B9~NOT = LCELL(!rest);
-- Node name is ':50'
-- Equation name is '_LC4_B9', type is buried
_LC4_B9 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, !_LC1_B9);
_EQ009 = _LC4_B9 & load
# data7 & !load;
Project Information f:\zuixin\bingxingru.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 43,932K
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