dizishengcheng.v

来自「这是一个信号发生器得程序」· Verilog 代码 · 共 16 行

module dizishengcheng(clk,wren,,wraddress,zhongduan);
input clk,wren;
output [10:0] wraddress;
output zhongduan;
reg zhongduan;
reg [10:0] wraddress;
always@(posedge clk )
if (wren)
wraddress<=wraddress+1;
always@(posedge clk)
if(wraddress==2047)
zhongduan=1;
endmodule