📄 dizishengcheng.v
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module dizishengcheng(clk,wren,,wraddress,zhongduan);
input clk,wren;
output [10:0] wraddress;
output zhongduan;
reg zhongduan;
reg [10:0] wraddress;
always@(posedge clk )
if (wren)
wraddress<=wraddress+1;
always@(posedge clk)
if(wraddress==2047)
zhongduan=1;
endmodule
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