📄 diziduqu.rpt
字号:
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\zuixin\diziduqu.rpt
diziduqu
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 8/ 96( 8%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zuixin\diziduqu.rpt
diziduqu
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 11 clk
Device-Specific Information: f:\zuixin\diziduqu.rpt
diziduqu
** EQUATIONS **
clk : INPUT;
rden : INPUT;
-- Node name is 'rdaddress0'
-- Equation name is 'rdaddress0', type is output
rdaddress0 = _LC5_C9;
-- Node name is 'rdaddress1'
-- Equation name is 'rdaddress1', type is output
rdaddress1 = _LC6_C9;
-- Node name is 'rdaddress2'
-- Equation name is 'rdaddress2', type is output
rdaddress2 = _LC1_C9;
-- Node name is 'rdaddress3'
-- Equation name is 'rdaddress3', type is output
rdaddress3 = _LC7_C9;
-- Node name is 'rdaddress4'
-- Equation name is 'rdaddress4', type is output
rdaddress4 = _LC3_C9;
-- Node name is 'rdaddress5'
-- Equation name is 'rdaddress5', type is output
rdaddress5 = _LC4_C9;
-- Node name is 'rdaddress6'
-- Equation name is 'rdaddress6', type is output
rdaddress6 = _LC5_C5;
-- Node name is 'rdaddress7'
-- Equation name is 'rdaddress7', type is output
rdaddress7 = _LC7_C5;
-- Node name is 'rdaddress8'
-- Equation name is 'rdaddress8', type is output
rdaddress8 = _LC2_C5;
-- Node name is 'rdaddress9'
-- Equation name is 'rdaddress9', type is output
rdaddress9 = _LC1_C5;
-- Node name is 'rdaddress10'
-- Equation name is 'rdaddress10', type is output
rdaddress10 = _LC3_C5;
-- Node name is '|lpm_add_sub:37|addcore:adder|:87' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C9', type is buried
_LC8_C9 = LCELL( _EQ001);
_EQ001 = _LC1_C9 & _LC5_C9 & _LC6_C9;
-- Node name is '|lpm_add_sub:37|addcore:adder|:91' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_C9', type is buried
_LC2_C9 = LCELL( _EQ002);
_EQ002 = _LC7_C9 & _LC8_C9;
-- Node name is '|lpm_add_sub:37|addcore:adder|:99' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_C5', type is buried
_LC4_C5 = LCELL( _EQ003);
_EQ003 = _LC3_C9 & _LC4_C9 & _LC7_C9 & _LC8_C9;
-- Node name is '|lpm_add_sub:37|addcore:adder|:103' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C5', type is buried
_LC6_C5 = LCELL( _EQ004);
_EQ004 = _LC4_C5 & _LC5_C5;
-- Node name is '|lpm_add_sub:37|addcore:adder|:111' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_C5', type is buried
_LC8_C5 = LCELL( _EQ005);
_EQ005 = _LC2_C5 & _LC4_C5 & _LC5_C5 & _LC7_C5;
-- Node name is ':15'
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, rden);
_EQ006 = !_LC1_C5 & _LC3_C5
# _LC3_C5 & !_LC8_C5
# _LC1_C5 & !_LC3_C5 & _LC8_C5;
-- Node name is ':16'
-- Equation name is '_LC1_C5', type is buried
_LC1_C5 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, rden);
_EQ007 = _LC1_C5 & !_LC8_C5
# !_LC1_C5 & _LC8_C5;
-- Node name is ':17'
-- Equation name is '_LC2_C5', type is buried
_LC2_C5 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, rden);
_EQ008 = _LC2_C5 & !_LC6_C5
# _LC2_C5 & !_LC7_C5
# !_LC2_C5 & _LC6_C5 & _LC7_C5;
-- Node name is ':18'
-- Equation name is '_LC7_C5', type is buried
_LC7_C5 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, rden);
_EQ009 = !_LC5_C5 & _LC7_C5
# !_LC4_C5 & _LC7_C5
# _LC4_C5 & _LC5_C5 & !_LC7_C5;
-- Node name is ':19'
-- Equation name is '_LC5_C5', type is buried
_LC5_C5 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, rden);
_EQ010 = !_LC4_C5 & _LC5_C5
# _LC4_C5 & !_LC5_C5;
-- Node name is ':20'
-- Equation name is '_LC4_C9', type is buried
_LC4_C9 = DFFE( _EQ011, GLOBAL( clk), VCC, VCC, rden);
_EQ011 = !_LC2_C9 & _LC4_C9
# !_LC3_C9 & _LC4_C9
# _LC2_C9 & _LC3_C9 & !_LC4_C9;
-- Node name is ':21'
-- Equation name is '_LC3_C9', type is buried
_LC3_C9 = DFFE( _EQ012, GLOBAL( clk), VCC, VCC, rden);
_EQ012 = _LC3_C9 & !_LC7_C9
# _LC3_C9 & !_LC8_C9
# !_LC3_C9 & _LC7_C9 & _LC8_C9;
-- Node name is ':22'
-- Equation name is '_LC7_C9', type is buried
_LC7_C9 = DFFE( _EQ013, GLOBAL( clk), VCC, VCC, rden);
_EQ013 = _LC7_C9 & !_LC8_C9
# !_LC7_C9 & _LC8_C9;
-- Node name is ':23'
-- Equation name is '_LC1_C9', type is buried
_LC1_C9 = DFFE( _EQ014, GLOBAL( clk), VCC, VCC, rden);
_EQ014 = _LC1_C9 & !_LC6_C9
# _LC1_C9 & !_LC5_C9
# !_LC1_C9 & _LC5_C9 & _LC6_C9;
-- Node name is ':24'
-- Equation name is '_LC6_C9', type is buried
_LC6_C9 = DFFE( _EQ015, GLOBAL( clk), VCC, VCC, rden);
_EQ015 = !_LC5_C9 & _LC6_C9
# _LC5_C9 & !_LC6_C9;
-- Node name is ':25'
-- Equation name is '_LC5_C9', type is buried
_LC5_C9 = DFFE(!_LC5_C9, GLOBAL( clk), VCC, VCC, rden);
Project Information f:\zuixin\diziduqu.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 39,598K
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