bingxingru.v

来自「这是一个信号发生器得程序」· Verilog 代码 · 共 22 行

module bingxingru(clk,rest,load,dout,N);
input [7:0]N;
input clk,rest;
input load;
reg [7:0] data;
wire clk,rest;
output dout;
reg dout;
always@(posedge clk or posedge rest )
begin
if (rest) data<=0;
else
if (load)
data<=N;
else  
begin
dout<=(data[7]);
data<=(data<<1);
end
end
endmodule