📄 2.4g+̤
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00EB 9A55 SBI 0x0A,5
(0231) nRF24L01_SCK_DIR;
00EC 9A57 SBI 0x0A,7
(0232) nRF24L01_CSN_DIR;
00ED 9A56 SBI 0x0A,6
(0233) nRF24L01_MOSI_DIR;
00EE 9A20 SBI 0x04,0
00EF 9508 RET
(0234) }
(0235) /*-----------------------------------------------------------------------------
(0236) Module: init_CPU
(0237) Function: Initialization of CPU
(0238) ------------------------------------------------------------------------------*/
(0239) void init_CPU (void)
(0240) {
(0241) MCUCR = 0x00; //
_init_CPU:
00F0 2422 CLR R2
00F1 BE25 OUT 0x35,R2
(0242) EICRA = 0x00; //extended ext ints
00F2 92200069 STS 0x69,R2
(0243) EIMSK = 0x00;
00F4 BA2D OUT 0x1D,R2
(0244)
(0245) TIMSK0 = 0x01; //timer 0 interrupt sources
00F5 E081 LDI R24,1
00F6 9380006E STS 0x6E,R24
(0246) TIMSK1 = 0x00; //timer 1 interrupt sources
00F8 9220006F STS 0x6F,R2
(0247) TIMSK2 = 0x00; //timer 2 interrupt sources
00FA 92200070 STS 0x70,R2
(0248) CLI(); //disable all interrupts
00FC 94F8 BCLR 7
(0249) NOP();
00FD 0000 NOP
(0250) PORTB = 0x01;
00FE B985 OUT 0x05,R24
(0251) DDRB = 0xf3;
00FF EF83 LDI R24,0xF3
0100 B984 OUT 0x04,R24
(0252) PORTD = 0x80;
0101 E880 LDI R24,0x80
0102 B98B OUT 0x0B,R24
(0253) DDRD = 0xE3;
0103 EE83 LDI R24,0xE3
0104 B98A OUT 0x0A,R24
(0254) PORTC = 0x80;
0105 E880 LDI R24,0x80
0106 B988 OUT 0x08,R24
(0255) DDRC = 0x40;
0107 E480 LDI R24,0x40
0108 B987 OUT 0x07,R24
(0256) nrf24l01init();
0109 DFDF RCALL _nrf24l01init
(0257) nRF24L01_CEL;
010A 985D CBI 0x0B,5
(0258) delay();
010B D005 RCALL _delay
(0259) nRF24L01_CSNH; // Spi disable
010C 9A5E SBI 0x0B,6
(0260) delay();
010D D003 RCALL _delay
(0261) nRF24L01_SCKL;
010E 985F CBI 0x0B,7
(0262) delay();
010F D001 RCALL _delay
0110 9508 RET
(0263) }
(0264) void delay(void)//
(0265) {
(0266) NOP();
_delay:
0111 0000 NOP
(0267) NOP();
0112 0000 NOP
(0268) NOP();
0113 0000 NOP
(0269) NOP();
0114 0000 NOP
(0270) NOP();
0115 0000 NOP
(0271) NOP();
0116 0000 NOP
0117 9508 RET
(0272) }
(0273) void delayms(unsigned short dly)//
(0274) {
(0275) for(;dly>0;dly--) ;
_delayms:
dly --> R16
0118 C002 RJMP 0x011B
0119 5001 SUBI R16,1
011A 4010 SBCI R17,0
011B 3000 CPI R16,0
011C 0701 CPC R16,R17
011D F7D9 BNE 0x0119
011E 9508 RET
(0276) }
(0277)
(0278) void clear_buf(unsigned char *ptr,unsigned char number)//清零buffer,指定字节个数
(0279) {
(0280) for (;number>0;number--) *ptr++=0;
_clear_buf:
number --> R18
ptr --> R16
011F C005 RJMP 0x0125
0120 2422 CLR R2
0121 01F8 MOVW R30,R16
0122 9221 ST R2,Z+
0123 018F MOVW R16,R30
0124 952A DEC R18
0125 2422 CLR R2
0126 1622 CP R2,R18
0127 F3C0 BCS 0x0120
0128 9508 RET
_SPI_RW:
bit_ctr --> R20
byte --> R22
0129 D2DD RCALL push_gset2
012A 2F60 MOV R22,R16
(0281) }
(0282) //------------------------------------------------------
(0283) /**************************************************
(0284) Function: SPI_RW();
(0285)
(0286) Description:
(0287) Writes one byte to nRF24L01, and return the byte read
(0288) from nRF24L01 during write, according to SPI protocol */
(0289) /**************************************************/
(0290) unsigned char SPI_RW(unsigned char byte)
(0291) {
(0292) unsigned char bit_ctr;
(0293) for(bit_ctr=0;bit_ctr<8;bit_ctr++) // output 8-bit
012B 2744 CLR R20
012C C00F RJMP 0x013C
(0294) {
(0295) if(byte & 0x80)
012D FF67 SBRS R22,7
012E C002 RJMP 0x0131
(0296) nRF24L01_MOSIH;
012F 9A28 SBI 0x05,0
0130 C001 RJMP 0x0132
(0297) else
(0298) nRF24L01_MOSIL;
0131 9828 CBI 0x05,0
(0299) delay();
0132 DFDE RCALL _delay
(0300) byte = (byte << 1); // shift next bit into MSB..
0133 0F66 LSL R22
(0301) nRF24L01_SCKH;
0134 9A5F SBI 0x0B,7
(0302) delay();
0135 DFDB RCALL _delay
(0303) if(PINB&nRF24L01_MISO) byte |= 1;
0136 9B19 SBIS 0x03,1
0137 C001 RJMP 0x0139
0138 6061 ORI R22,1
(0304) nRF24L01_SCKL;
0139 985F CBI 0x0B,7
(0305) delay();
013A DFD6 RCALL _delay
013B 9543 INC R20
013C 3048 CPI R20,0x8
013D F378 BCS 0x012D
(0306) }
(0307) return(byte); // return read byte
013E 2F06 MOV R16,R22
013F D2BD RCALL pop_gset2
0140 9508 RET
_SPI_RW_Reg:
status --> R20
value --> R22
reg --> R20
0141 D2C5 RCALL push_gset2
0142 2F62 MOV R22,R18
0143 2F40 MOV R20,R16
(0308) }
(0309) /**************************************************
(0310) Function: SPI_RW_Reg();
(0311)
(0312) Description:
(0313) Writes value 'value' to register 'reg' */
(0314) /**************************************************/
(0315) unsigned char SPI_RW_Reg(unsigned char reg, unsigned char value)
(0316) {
(0317) unsigned char status;
(0318) nRF24L01_CSNL;
0144 985E CBI 0x0B,6
(0319) delay();
0145 DFCB RCALL _delay
(0320) status = SPI_RW(reg); // select register
0146 2F04 MOV R16,R20
0147 DFE1 RCALL _SPI_RW
0148 2F40 MOV R20,R16
(0321) SPI_RW(value); // ..and write value to it..
0149 2F06 MOV R16,R22
014A DFDE RCALL _SPI_RW
(0322) nRF24L01_CSNH;
014B 9A5E SBI 0x0B,6
(0323) delay();
014C DFC4 RCALL _delay
(0324) return(status); // return nRF24L01 status byte
014D 2F04 MOV R16,R20
014E D2AE RCALL pop_gset2
014F 9508 RET
_SPI_Read:
reg_val --> R20
reg --> R20
0150 D2B8 RCALL push_gset1
0151 2F40 MOV R20,R16
(0325) }
(0326) /**************************************************
(0327) Function: SPI_Read();
(0328)
(0329) Description:
(0330) Read one byte from nRF24L01 register, 'reg' */
(0331) /**************************************************/
(0332) unsigned char SPI_Read(unsigned char reg)
(0333) {
(0334) unsigned char reg_val;
(0335) nRF24L01_CSNL;
0152 985E CBI 0x0B,6
(0336) delay();
0153 DFBD RCALL _delay
(0337) SPI_RW(reg); // Select register to read from..
0154 2F04 MOV R16,R20
0155 DFD3 RCALL _SPI_RW
(0338) reg_val = SPI_RW(0); // ..then read registervalue
0156 2700 CLR R16
0157 DFD1 RCALL _SPI_RW
0158 2F40 MOV R20,R16
(0339) nRF24L01_CSNH;
0159 9A5E SBI 0x0B,6
(0340) delay();
015A DFB6 RCALL _delay
(0341) return(reg_val); // return register value
015B 2F04 MOV R16,R20
015C D2AF RCALL pop_gset1
015D 9508 RET
_SPI_Read_Buf:
status --> R20
byte_ctr --> R22
bytes --> R10
pBuf --> R12
reg --> R20
015E D2A4 RCALL push_gset4
015F 0169 MOVW R12,R18
0160 2F40 MOV R20,R16
0161 84A8 LDD R10,Y+8
(0342) }
(0343) /**************************************************
(0344) Function: SPI_Read_Buf();
(0345)
(0346) Description:
(0347) Reads 'bytes' #of bytes from register 'reg'
(0348) Typically used to read RX payload, Rx/Tx address */
(0349) /**************************************************/
(0350) unsigned char SPI_Read_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes)
(0351) {
(0352) unsigned char status,byte_ctr;
(0353) nRF24L01_CSNL;
0162 985E CBI 0x0B,6
(0354) delay();
0163 DFAD RCALL _delay
(0355) status = SPI_RW(reg); // Select register to write to and read status byte
0164 2F04 MOV R16,R20
0165 DFC3 RCALL _SPI_RW
0166 2F40 MOV R20,R16
(0356) for(byte_ctr=0;byte_ctr<bytes;byte_ctr++)
0167 2766 CLR R22
0168 C008 RJMP 0x0171
(0357) pBuf[byte_ctr] = SPI_RW(0); // Perform SPI_RW to read byte from nRF24L01
0169 2700 CLR R16
016A DFBE RCALL _SPI_RW
016B 2FE6 MOV R30,R22
016C 27FF CLR R31
016D 0DEC ADD R30,R12
016E 1DFD ADC R31,R13
016F 8300 STD Z+0,R16
0170 9563 INC R22
0171 156A CP R22,R10
0172 F3B0 BCS 0x0169
(0358) nRF24L01_CSNH;
0173 9A5E SBI 0x0B,6
(0359) delay();
0174 DF9C RCALL _delay
(0360) return(status); // return nRF24L01 status byte
0175 2F04 MOV R16,R20
0176 D288 RCALL pop_gset4
0177 9508 RET
_SPI_Write_Buf:
status --> R20
byte_ctr --> R22
bytes --> R10
pBuf --> R12
reg --> R20
0178 D28A RCALL push_gset4
0179 0169 MOVW R12,R18
017A 2F40 MOV R20,R16
017B 84A8 LDD R10,Y+8
(0361) }
(0362) /**************************************************
(0363) Function: SPI_Write_Buf();
(0364)
(0365) Description:
(0366) Writes contents of buffer '*pBuf' to nRF24L01
(0367) Typically used to write TX payload, Rx/Tx address */
(0368) /**************************************************/
(0369) unsigned char SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes)
(0370) {
(0371) unsigned char status,byte_ctr;
(0372) nRF24L01_CSNL; // Set nRF24L01_CSN low, init SPI tranaction
017C 985E CBI 0x0B,6
(0373) delay();
017D DF93 RCALL _delay
(0374) status = SPI_RW(reg); // Select register to write to and read status byte
017E 2F04 MOV R16,R20
017F DFA9 RCALL _SPI_RW
0180 2F40 MOV R20,R16
(0375) for(byte_ctr=0; byte_ctr<bytes; byte_ctr++) // then write all byte in buffer(*pBuf)
0181 2766 CLR R22
0182 C006 RJMP 0x0189
(0376) status = SPI_RW(*pBuf++);
0183 01F6 MOVW R30,R12
0184 9101 LD R16,Z+
0185 016F MOVW R12,R30
0186 DFA2 RCALL _SPI_RW
0187 2F40 MOV R20,R16
0188 9563 INC R22
0189 156A CP R22,R10
018A F3C0 BCS 0x0183
(0377) nRF24L01_CSNH; // Set nRF24L01_CSN high again
018B 9A5E SBI 0x0B,6
(0378) delay();
018C DF84 RCALL _delay
(0379) return(status); // return nRF24L01 status byte
018D 2F04 MOV R16,R20
018E D270 RCALL pop_gset4
018F 9508 RET
_RX_Mode:
0190 9721 SBIW R28,1
(0380) }
(0381) /**************************************************
(0382) Function: RX_Mode();
(0383)
(0384) Description:
(0385) This function initializes one nRF24L01 device to
(0386) RX Mode, set RX address, writes RX payload width,
(0387) select RF channel, datarate & LNA HCURR.
(0388) After init, CE is toggled high, which means that
(0389) this device is now ready to receive a datapacket. */
(0390) /**************************************************/
(0391) void RX_Mode(void)
(0392) {
(0393) nRF24L01_CEL;
0191 985D CBI 0x0B,5
(0394) delay();
0192 DF7E RCALL _delay
(0395) SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // Use the same address on the RX device as the TX device
0193 E085 LDI R24,5
0194 8388 STD Y+0,R24
0195 E420 LDI R18,0x40
0196 E031 LDI R19,1
0197 E20A LDI R16,0x2A
0198 DFDF RCALL _SPI_Write_Buf
(0396)
(0397) SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
0199 E021 LDI R18,1
019A E201 LDI R16,0x21
019B DFA5 RCALL _SPI_RW_Reg
(0398) SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
019C E021 LDI R18,1
019D E202 LDI R16,0x22
019E DFA2 RCALL _SPI_RW_Reg
(0399) SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40
019F E228 LDI R18,0x28
01A0 E205 LDI R16,0x25
01A1 DF9F RCALL _SPI_RW_Reg
(0400) SPI_RW_Reg(WRITE_REG + RX_PW_P0, TX_PLOAD_WIDTH); // Select same RX payload width as TX Payload width
01A2 E124 LDI R18,0x14
01A3 E301 LDI R16,0x31
01A4 DF9C RCALL _SPI_RW_Reg
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