2.4g+̤

2.4G无线模块资料

__start:
__text_start:
    003F EFCF      LDI	R28,0xFF
    0040 E0D2      LDI	R29,2
    0041 BFCD      OUT	0x3D,R28
    0042 BFDE      OUT	0x3E,R29
    0043 51C0      SUBI	R28,0x10
    0044 40D0      SBCI	R29,0
    0045 EA0A      LDI	R16,0xAA
    0046 8308      STD	Y+0,R16
    0047 2400      CLR	R0
    0048 E4E9      LDI	R30,0x49
    0049 E0F1      LDI	R31,1
    004A E011      LDI	R17,1
    004B 36E5      CPI	R30,0x65
    004C 07F1      CPC	R31,R17
    004D F011      BEQ	0x0050
    004E 9201      ST	R0,Z+
    004F CFFB      RJMP	0x004B
    0050 8300      STD	Z+0,R16
    0051 E3E4      LDI	R30,0x34
    0052 E0F0      LDI	R31,0
    0053 E0A0      LDI	R26,0
    0054 E0B1      LDI	R27,1
    0055 E010      LDI	R17,0
    0056 37ED      CPI	R30,0x7D
    0057 07F1      CPC	R31,R17
    0058 F021      BEQ	0x005D
    0059 95C8      LPM
    005A 9631      ADIW	R30,1
    005B 920D      ST	R0,X+
    005C CFF9      RJMP	0x0056
    005D D001      RCALL	_main
_exit:
    005E CFFF      RJMP	_exit
_main:
  Get_SO               --> R20
    005F 9721      SBIW	R28,1
FILE: E:\项目\PS2无~1\progamme\sendavrnrf24l01\sendavrnrf24l01\main.c
(0001) //ICC-AVR application builder : 2006-02-12 14:00:00
(0002) // Target : ATmega48
(0003) // Crystal: 8.000Mhz
(0004) // Author:  jackyan
(0005) // Oled Type : white
(0006) //#define fosc 8000000
(0007) //#define baud 9600
(0008) #include "iom48v.h"
(0009) #include "macros.h"
(0010) #include "defs.h"
(0011) /*-----------------------------------------------------------------------------
(0012)    Global Defines
(0013) ------------------------------------------------------------------------------*/
(0014) unsigned char   key_debug;
(0015) unsigned char 	Buffer[]={
(0016) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0017) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0018) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0019) 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
(0020) };
(0021) #define TX_ADR_WIDTH    5   // 5 bytes TX(RX) address width
(0022) #define TX_PLOAD_WIDTH  20  // 16 bytes TX payload
(0023) unsigned char TX_ADDRESS[TX_ADR_WIDTH]  = {0x34,0x43,0x10,0x10,0x01}; // Define a static TX address
(0024) void init_CPU (void);
(0025) void delayms(unsigned short	dly);//当dly=1时，延时的时间是1ms  4MHz晶震
(0026) void INIT_io(void);
(0027) void RX_Mode(void);
(0028) void TX_Mode(void);
(0029) void delay(void);
(0030) unsigned char SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
(0031) unsigned char SPI_Read_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
(0032) unsigned char SPI_RW_Reg(unsigned char reg, unsigned char value);
(0033) unsigned char SPI_Read(unsigned char reg);
(0034) void clear_buf(unsigned char	*ptr,unsigned char number);
(0035) unsigned char accept_flag=0;
(0036) unsigned char send_flag=0;
(0037) unsigned int accept_time=0;
(0038) void nrf24l01init(void);
(0039) void timer0_init(void);
(0040) //****************************************************************//
(0041) // SPI(nRF24L01) commands
(0042) #define READ_REG        0x00  // Define read command to register
(0043) #define WRITE_REG       0x20  // Define write command to register
(0044) #define RD_RX_PLOAD     0x61  // Define RX payload register address
(0045) #define WR_TX_PLOAD     0xA0  // Define TX payload register address
(0046) #define FLUSH_TX        0xE1  // Define flush TX register command
(0047) #define FLUSH_RX        0xE2  // Define flush RX register command
(0048) #define REUSE_TX_PL     0xE3  // Define reuse TX payload register command
(0049) //#define NOP             0xFF  // Define No Operation, might be used to read status register
(0050) //***************************************************//
(0051) // SPI(nRF24L01) registers(addresses)
(0052) #define CONFIG          0x00  // 'Config' register address
(0053) #define EN_AA           0x01  // 'Enable Auto Acknowledgment' register address
(0054) #define EN_RXADDR       0x02  // 'Enabled RX addresses' register address
(0055) #define SETUP_AW        0x03  // 'Setup address width' register address
(0056) #define SETUP_RETR      0x04  // 'Setup Auto. Retrans' register address
(0057) #define RF_CH           0x05  // 'RF channel' register address
(0058) #define RF_SETUP        0x06  // 'RF setup' register address
(0059) #define STATUS          0x07  // 'Status' register address
(0060) #define OBSERVE_TX      0x08  // 'Observe TX' register address
(0061) #define CD              0x09  // 'Carrier Detect' register address
(0062) #define RX_ADDR_P0      0x0A  // 'RX address pipe0' register address
(0063) #define RX_ADDR_P1      0x0B  // 'RX address pipe1' register address
(0064) #define RX_ADDR_P2      0x0C  // 'RX address pipe2' register address
(0065) #define RX_ADDR_P3      0x0D  // 'RX address pipe3' register address
(0066) #define RX_ADDR_P4      0x0E  // 'RX address pipe4' register address
(0067) #define RX_ADDR_P5      0x0F  // 'RX address pipe5' register address
(0068) #define TX_ADDR         0x10  // 'TX address' register address
(0069) #define RX_PW_P0        0x11  // 'RX payload width, pipe0' register address
(0070) #define RX_PW_P1        0x12  // 'RX payload width, pipe1' register address
(0071) #define RX_PW_P2        0x13  // 'RX payload width, pipe2' register address
(0072) #define RX_PW_P3        0x14  // 'RX payload width, pipe3' register address
(0073) #define RX_PW_P4        0x15  // 'RX payload width, pipe4' register address
(0074) #define RX_PW_P5        0x16  // 'RX payload width, pipe5' register address
(0075) #define FIFO_STATUS     0x17  // 'FIFO Status Register' register address
(0076) #define MAX_RT  	0x10  // Max #of TX retrans interrupt
(0077) #define TX_DS   	0x20  // TX data sent interrupt
(0078) #define RX_DR   	0x40  // RX data received
(0079) //-----------------------------------------------------------------------------
(0080) //------------------------------------------------------
(0081) unsigned char t20ms;
(0082) #define BIT(x)	           (1 << (x))
(0083) #define SETBIT(x, y)   	   (x |= y)
(0084) #define CLEARBIT(x, y) 	   (x &= ~y)
(0085) #define CHECKBIT(x, y) 	   (x & y)
(0086) #define BIT7 0x80
(0087) #define BIT6 0x40
(0088) #define BIT5 0x20
(0089) #define BIT4 0x10
(0090) #define BIT3 0x08
(0091) #define BIT2 0x04
(0092) #define BIT1 0x02
(0093) #define BIT0 0x01
(0094) #define nRF24L01_CSN        BIT6
(0095) #define nRF24L01_SCK        BIT7
(0096) #define nRF24L01_MOSI       BIT0
(0097) #define nRF24L01_CE         BIT5   
(0098) #define nRF24L01_MISO 	    BIT1
(0099) #define nRF24L01_IRQ  	    BIT2
(0100) #define nRF24L01_CSNH       SETBIT(PORTD, nRF24L01_CSN)     
(0101) #define nRF24L01_CSNL       CLEARBIT(PORTD, nRF24L01_CSN)   
(0102) 
(0103) #define nRF24L01_CSN_DIR    SETBIT(DDRD, nRF24L01_CSN)  //OUTPUT
(0104) 
(0105) #define nRF24L01_SCKH       SETBIT(PORTD,nRF24L01_SCK)      
(0106) #define nRF24L01_SCKL       CLEARBIT(PORTD,nRF24L01_SCK)    
(0107) #define nRF24L01_SCK_DIR   SETBIT(DDRD,nRF24L01_SCK)  //OUTPUT
(0108)  
(0109) #define nRF24L01_MOSIH      SETBIT(PORTB,nRF24L01_MOSI)     
(0110) #define nRF24L01_MOSIL	    CLEARBIT(PORTB,nRF24L01_MOSI)   
(0111) #define nRF24L01_MOSI_DIR   SETBIT(DDRB,nRF24L01_MOSI)
(0112) 
(0113) #define nRF24L01_CEH        SETBIT(PORTD,nRF24L01_CE)  //OUTPUT   
(0114) #define nRF24L01_CEL        CLEARBIT(PORTD,nRF24L01_CE)
(0115) #define nRF24L01_CE_DIR     SETBIT(DDRD,nRF24L01_CE)
(0116) 
(0117) #define nRF24L01_IRQ_DIR     CLEARBIT(DDRB,nRF24L01_IRQ) //INPUT
(0118) 
(0119) #define nRF24L01_MISO_DIR    CLEARBIT(DDRB,nRF24L01_MISO) //INPUT
(0120) #define key1 	BIT4
(0121) #define key2 	BIT3
(0122) #define key3 	BIT2
(0123) #define key4 	BIT5
(0124) #define key5 	BIT4
(0125) #define key6 	BIT3
(0126) #define key7 	BIT2
(0127) #define key8 	BIT1
(0128) #define 	bit20ms 					BIT0
(0129) unsigned char flag;
(0130) unsigned char key1_pulse;
(0131) unsigned char key2_pulse;
(0132) unsigned char key3_pulse;
(0133) unsigned char key4_pulse;
(0134) unsigned char key5_pulse;
(0135) unsigned char key6_pulse;
(0136) unsigned char key7_pulse;
(0137) unsigned char key8_pulse;
(0138) unsigned char key1_flag;
(0139) unsigned char key2_flag;
(0140) unsigned char key3_flag;
(0141) unsigned char key4_flag;
(0142) unsigned char key5_flag;
(0143) unsigned char key6_flag;
(0144) unsigned char key7_flag;
(0145) unsigned char key8_flag;
(0146) unsigned char key8_long_flag;
(0147) unsigned char send_flag;
(0148) unsigned char key1_time;
(0149) unsigned char key2_time;
(0150) unsigned char key3_time;
(0151) unsigned char key4_time;
(0152) unsigned char key5_time;
(0153) unsigned char key6_time;
(0154) unsigned char key7_time;
(0155) unsigned char key8_time;
(0156) //-----------------------------------------------------------------------------
(0157) void main(void)
(0158) {
(0159)  	unsigned char Get_SO=0;
    0060 2744      CLR	R20
(0160)     CLI();                   /* global interrupt disable */
    0061 94F8      BCLR	7
(0161)     init_CPU ();
    0062 D08D      RCALL	_init_CPU
(0162)     delayms(100);	//延时10ms*10=100ms
    0063 E604      LDI	R16,0x64
    0064 E010      LDI	R17,0
    0065 D0B2      RCALL	_delayms
(0163)     delayms(100);	//延时10ms*10=100ms
    0066 E604      LDI	R16,0x64
    0067 E010      LDI	R17,0
    0068 D0AF      RCALL	_delayms
(0164) 	timer0_init();
    0069 D170      RCALL	_timer0_init
(0165) 	RX_Mode();
    006A D125      RCALL	_RX_Mode
(0166) 	SEI();
    006B 9478      BSET	7
    006C C079      RJMP	0x00E6
(0167) 	while(1)
(0168) 	{		
(0169) 		//	if(!(PINB& 0x01))
(0170) 		WDR();
    006D 95A8      WDR
(0171) 		if(!(PINB& nRF24L01_IRQ))
    006E 991A      SBIC	0x03,2
    006F C022      RJMP	0x0092
(0172) 		{//nRF24L01 接收数据
(0173) 			key_debug=SPI_Read(STATUS);			// read register STATUS's value
    0070 E007      LDI	R16,7
    0071 D0DE      RCALL	_SPI_Read
    0072 93000164  STS	key_debug,R16
(0174) 			if(key_debug&RX_DR)					// if renRF24L01_CEive data ready (RX_DR) interrupt
    0074 FF06      SBRS	R16,6
    0075 C006      RJMP	0x007C
(0175) 				SPI_Read_Buf(RD_RX_PLOAD,Buffer,TX_PLOAD_WIDTH);// read renRF24L01_CEive payload from RX_FIFO buffer
    0076 E184      LDI	R24,0x14
    0077 8388      STD	Y+0,R24
    0078 E020      LDI	R18,0
    0079 E031      LDI	R19,1
    007A E601      LDI	R16,0x61
    007B D0E2      RCALL	_SPI_Read_Buf
(0176) 			if(key_debug&MAX_RT) SPI_RW_Reg(FLUSH_TX,0);
    007C 90200164  LDS	R2,key_debug
    007E FE24      SBRS	R2,4
    007F C003      RJMP	0x0083
    0080 2722      CLR	R18
    0081 EE01      LDI	R16,0xE1
    0082 D0BE      RCALL	_SPI_RW_Reg
(0177) 			SPI_RW_Reg(WRITE_REG+STATUS,0xff);// clear RX_DR or TX_DS or MAX_RT interrupt flag
    0083 EF2F      LDI	R18,0xFF
    0084 E207      LDI	R16,0x27
    0085 D0BB      RCALL	_SPI_RW_Reg
(0178) 			RX_Mode();
    0086 D109      RCALL	_RX_Mode
(0179) 			if((Buffer[0]==80)&&(Buffer[1]==01))//data accept
    0087 91800100  LDS	R24,Buffer
    0089 3580      CPI	R24,0x50
    008A F439      BNE	0x0092
    008B 91800101  LDS	R24,Buffer+1
    008D 3081      CPI	R24,1
    008E F419      BNE	0x0092
(0180) 			{
(0181) 			 	accept_flag=1;
    008F E081      LDI	R24,1
    0090 93800145  STS	accept_flag,R24
(0182) 			}
(0183) 		}
(0184) 		if(send_flag==1)//data send
    0092 91800146  LDS	R24,send_flag
    0094 3081      CPI	R24,1
    0095 F481      BNE	0x00A6
(0185) 		{
(0186) 		 		Buffer[0]=80;
    0096 E580      LDI	R24,0x50
    0097 93800100  STS	Buffer,R24
(0187) 				Buffer[1]=02;
    0099 E082      LDI	R24,2
    009A 93800101  STS	Buffer+1,R24
(0188) 				TX_Mode();			// set TX Mode and transmitting
    009C D112      RCALL	_TX_Mode
(0189) 				delayms(100);
    009D E604      LDI	R16,0x64
    009E E010      LDI	R17,0
    009F D078      RCALL	_delayms
(0190) 				RX_Mode();
    00A0 D0EF      RCALL	_RX_Mode
(0191) 				Buffer[0]=00;
    00A1 2422      CLR	R2
    00A2 92200100  STS	Buffer,R2
(0192) 				Buffer[1]=00;
    00A4 92200101  STS	Buffer+1,R2
(0193) 		}
(0194) //========================================数据一直发送
(0195) 		if(key8_long_flag==1)//data send
    00A6 91800151  LDS	R24,key8_long_flag
    00A8 3081      CPI	R24,1
    00A9 F481      BNE	0x00BA
(0196) 		{
(0197) 		 		Buffer[0]=80;
    00AA E580      LDI	R24,0x50
    00AB 93800100  STS	Buffer,R24
(0198) 				Buffer[1]=02;
    00AD E082      LDI	R24,2
    00AE 93800101  STS	Buffer+1,R24
(0199) 				TX_Mode();			// set TX Mode and transmitting
    00B0 D0FE      RCALL	_TX_Mode
(0200) 				delayms(100);
    00B1 E604      LDI	R16,0x64
    00B2 E010      LDI	R17,0
    00B3 D064      RCALL	_delayms
(0201) 				RX_Mode();
    00B4 D0DB      RCALL	_RX_Mode
(0202) 				Buffer[0]=00;
    00B5 2422      CLR	R2
    00B6 92200100  STS	Buffer,R2
(0203) 				Buffer[1]=00;
    00B8 92200101  STS	Buffer+1,R2
(0204) 		}
(0205) //========================================数据一直发送
(0206) 		if(send_flag==1)
    00BA 91800146  LDS	R24,send_flag
    00BC 3081      CPI	R24,1
    00BD F4D1      BNE	0x00D8
(0207) 		{
(0208) 		   accept_time++;
    00BE 91800147  LDS	R24,accept_time
    00C0 91900148  LDS	R25,accept_time+1
    00C2 9601      ADIW	R24,1
    00C3 93900148  STS	accept_time+1,R25
    00C5 93800147  STS	accept_time,R24
(0209) 		   if(accept_time>30)
    00C7 E18E      LDI	R24,0x1E
    00C8 E090      LDI	R25,0
    00C9 90200147  LDS	R2,accept_time
    00CB 90300148  LDS	R3,accept_time+1
    00CD 1582      CP	R24,R2
    00CE 0593      CPC	R25,R3
    00CF F440      BCC	0x00D8
(0210) 		   {
(0211) 		   	 send_flag=0;
    00D0 2422      CLR	R2
    00D1 92200146  STS	send_flag,R2
(0212) 			 accept_time=0;
    00D3 2433      CLR	R3
    00D4 92300148  STS	accept_time+1,R3
    00D6 92200147  STS	accept_time,R2
(0213) 		   }
(0214) 		}
(0215) 		if(accept_flag==1)
    00D8 91800145  LDS	R24,accept_flag
    00DA 3081      CPI	R24,1
    00DB F451      BNE	0x00E6
(0216) 		{
(0217) 		    accept_flag=0;
    00DC 2422      CLR	R2
    00DD 92200145  STS	accept_flag,R2
(0218)     	 	PORTB = 0x80;
    00DF E880      LDI	R24,0x80
    00E0 B985      OUT	0x05,R24
(0219) 		    delayms(5000);	//延时10ms*10=100ms
    00E1 E808      LDI	R16,0x88
    00E2 E113      LDI	R17,0x13
    00E3 D034      RCALL	_delayms
(0220) 		    PORTB = 0x00;
    00E4 2422      CLR	R2
    00E5 B825      OUT	0x05,R2
    00E6 CF86      RJMP	0x006D
    00E7 9621      ADIW	R28,1
    00E8 9508      RET
(0221) 		}
(0222) 	}
(0223) 
(0224) 
(0225) }
(0226) void nrf24l01init(void)
(0227) {
(0228)  	 nRF24L01_IRQ_DIR;
_nrf24l01init:
    00E9 9822      CBI	0x04,2
(0229) 	 nRF24L01_MISO_DIR;
    00EA 9821      CBI	0x04,1
(0230) 	 nRF24L01_CE_DIR;