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//ICC-AVR application builder : 2006-02-12 14:00:00
// Target : ATmega48
// Crystal: 8.000Mhz
// Author: jackyan
// Oled Type : white
//#define fosc 8000000
//#define baud 9600
#include "iom48v.h"
#include "macros.h"
#include "defs.h"
/*-----------------------------------------------------------------------------
Global Defines
------------------------------------------------------------------------------*/
unsigned char key_debug;
unsigned char Buffer[]={
0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
};
#define TX_ADR_WIDTH 5 // 5 bytes TX(RX) address width
#define TX_PLOAD_WIDTH 20 // 16 bytes TX payload
unsigned char TX_ADDRESS[TX_ADR_WIDTH] = {0x34,0x43,0x10,0x10,0x01}; // Define a static TX address
void init_CPU (void);
void delayms(unsigned short dly);//当dly=1时，延时的时间是1ms 4MHz晶震
void INIT_io(void);
void RX_Mode(void);
void TX_Mode(void);
void delay(void);
unsigned char SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
unsigned char SPI_Read_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
unsigned char SPI_RW_Reg(unsigned char reg, unsigned char value);
unsigned char SPI_Read(unsigned char reg);
void clear_buf(unsigned char *ptr,unsigned char number);
unsigned char accept_flag=0;
unsigned char send_flag=0;
unsigned int accept_time=0;
void nrf24l01init(void);
//****************************************************************//
// SPI(nRF24L01) commands
#define READ_REG 0x00 // Define read command to register
#define WRITE_REG 0x20 // Define write command to register
#define RD_RX_PLOAD 0x61 // Define RX payload register address
#define WR_TX_PLOAD 0xA0 // Define TX payload register address
#define FLUSH_TX 0xE1 // Define flush TX register command
#define FLUSH_RX 0xE2 // Define flush RX register command
#define REUSE_TX_PL 0xE3 // Define reuse TX payload register command
//#define NOP 0xFF // Define No Operation, might be used to read status register
//***************************************************//
// SPI(nRF24L01) registers(addresses)
#define CONFIG 0x00 // 'Config' register address
#define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address
#define EN_RXADDR 0x02 // 'Enabled RX addresses' register address
#define SETUP_AW 0x03 // 'Setup address width' register address
#define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address
#define RF_CH 0x05 // 'RF channel' register address
#define RF_SETUP 0x06 // 'RF setup' register address
#define STATUS 0x07 // 'Status' register address
#define OBSERVE_TX 0x08 // 'Observe TX' register address
#define CD 0x09 // 'Carrier Detect' register address
#define RX_ADDR_P0 0x0A // 'RX address pipe0' register address
#define RX_ADDR_P1 0x0B // 'RX address pipe1' register address
#define RX_ADDR_P2 0x0C // 'RX address pipe2' register address
#define RX_ADDR_P3 0x0D // 'RX address pipe3' register address
#define RX_ADDR_P4 0x0E // 'RX address pipe4' register address
#define RX_ADDR_P5 0x0F // 'RX address pipe5' register address
#define TX_ADDR 0x10 // 'TX address' register address
#define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address
#define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address
#define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address
#define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address
#define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address
#define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address
#define FIFO_STATUS 0x17 // 'FIFO Status Register' register address
#define MAX_RT 0x10 // Max #of TX retrans interrupt
#define TX_DS 0x20 // TX data sent interrupt
#define RX_DR 0x40 // RX data received
//-----------------------------------------------------------------------------
//------------------------------------------------------
unsigned char t20ms;
#define BIT(x) (1 << (x))
#define SETBIT(x, y) (x |= y)
#define CLEARBIT(x, y) (x &= ~y)
#define CHECKBIT(x, y) (x & y)
#define BIT7 0x80
#define BIT6 0x40
#define BIT5 0x20
#define BIT4 0x10
#define BIT3 0x08
#define BIT2 0x04
#define BIT1 0x02
#define BIT0 0x01
#define nRF24L01_CSN BIT6
#define nRF24L01_SCK BIT7
#define nRF24L01_MOSI BIT0
#define nRF24L01_CE BIT5
#define nRF24L01_MISO BIT1
#define nRF24L01_IRQ BIT2
#define nRF24L01_CSNH SETBIT(PORTD, nRF24L01_CSN)
#define nRF24L01_CSNL CLEARBIT(PORTD, nRF24L01_CSN)
#define nRF24L01_CSN_DIR SETBIT(DDRD, nRF24L01_CSN) //OUTPUT
#define nRF24L01_SCKH SETBIT(PORTD,nRF24L01_SCK)
#define nRF24L01_SCKL CLEARBIT(PORTD,nRF24L01_SCK)
#define nRF24L01_SCK_DIR SETBIT(DDRD,nRF24L01_SCK) //OUTPUT
#define nRF24L01_MOSIH SETBIT(PORTB,nRF24L01_MOSI)
#define nRF24L01_MOSIL CLEARBIT(PORTB,nRF24L01_MOSI)
#define nRF24L01_MOSI_DIR SETBIT(DDRB,nRF24L01_MOSI)
#define nRF24L01_CEH SETBIT(PORTD,nRF24L01_CE) //OUTPUT
#define nRF24L01_CEL CLEARBIT(PORTD,nRF24L01_CE)
#define nRF24L01_CE_DIR SETBIT(DDRD,nRF24L01_CE)
#define nRF24L01_IRQ_DIR CLEARBIT(DDRB,nRF24L01_IRQ) //INPUT
#define nRF24L01_MISO_DIR CLEARBIT(DDRB,nRF24L01_MISO) //INPUT
#define key1 BIT5
#define key2 BIT6
#define key3 BIT7
#define key4 BIT0
#define key5 BIT1
#define key6 BIT2
#define bit20ms BIT0
unsigned char flag;
unsigned char key1_pulse;
unsigned char key2_pulse;
unsigned char key3_pulse;
unsigned char key4_pulse;
unsigned char key5_pulse;
unsigned char key6_pulse;
unsigned char key1_flag;
unsigned char key2_flag;
unsigned char key3_flag;
unsigned char key4_flag;
unsigned char key5_flag;
unsigned char key6_flag;
unsigned char send_flag;
unsigned char key1_time;
unsigned char key2_time;
unsigned char key3_time;
unsigned char key4_time;
unsigned char key5_time;
unsigned char key6_time;
//-----------------------------------------------------------------------------
void main(void)
{
unsigned char Get_SO=0;
CLI(); /* global interrupt disable */
init_CPU ();
delayms(100); //延时10ms*10=100ms
delayms(100); //延时10ms*10=100ms
RX_Mode();
send_flag=0;
while(1)
{
// if(!(PINB& 0x01))
WDR();
if(!(PINB& nRF24L01_IRQ))
{//nRF24L01 接收数据
key_debug=SPI_Read(STATUS); // read register STATUS's value
if(key_debug&RX_DR) // if renRF24L01_CEive data ready (RX_DR) interrupt
SPI_Read_Buf(RD_RX_PLOAD,Buffer,TX_PLOAD_WIDTH);// read renRF24L01_CEive payload from RX_FIFO buffer
if(key_debug&MAX_RT) SPI_RW_Reg(FLUSH_TX,0);
SPI_RW_Reg(WRITE_REG+STATUS,0xff);// clear RX_DR or TX_DS or MAX_RT interrupt flag
RX_Mode();
if((Buffer[0]==80)&&(Buffer[1]==02))//data accept
{
accept_flag=1;
// PORTB = 0x80;
// delayms(5000); //延时10ms*10=100ms
// PORTB = 0x00;
}
}
if(send_flag==1)
{
accept_time++;
if(accept_time>1000)
{
send_flag=0;
accept_time=0;
}
}
if(accept_flag==1)
{
accept_flag=0;
PORTB = 0x80;
delayms(1000); //延时10ms*10=100ms
PORTB = 0x00;
RX_Mode();
}
}
}
void nrf24l01init(void)
{
nRF24L01_IRQ_DIR;
nRF24L01_MISO_DIR;
nRF24L01_CE_DIR;
nRF24L01_SCK_DIR;
nRF24L01_CSN_DIR;
nRF24L01_MOSI_DIR;
}
/*-----------------------------------------------------------------------------
Module: init_CPU
Function: Initialization of CPU
------------------------------------------------------------------------------*/
void init_CPU (void)
{
MCUCR = 0x00; //
EICRA = 0x00; //extended ext ints
EIMSK = 0x00;
TIMSK0 = 0x01; //timer 0 interrupt sources
TIMSK1 = 0x00; //timer 1 interrupt sources
TIMSK2 = 0x00; //timer 2 interrupt sources
CLI(); //disable all interrupts
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