📄 2.4g+̤
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0148 1DFD ADC R31,R13
0149 8300 STD Z+0,R16
014A 9563 INC R22
014B 156A CP R22,R10
014C F3B0 BCS 0x0143
(0340) nRF24L01_CSNH;
014D 9A5E SBI 0x0B,6
(0341) delay();
014E DF9C RCALL _delay
(0342) return(status); // return nRF24L01 status byte
014F 2F04 MOV R16,R20
0150 D089 RCALL pop_gset4
0151 9508 RET
_SPI_Write_Buf:
status --> R20
byte_ctr --> R22
bytes --> R10
pBuf --> R12
reg --> R20
0152 D08B RCALL push_gset4
0153 0169 MOVW R12,R18
0154 2F40 MOV R20,R16
0155 84A8 LDD R10,Y+8
(0343) }
(0344) /**************************************************
(0345) Function: SPI_Write_Buf();
(0346)
(0347) Description:
(0348) Writes contents of buffer '*pBuf' to nRF24L01
(0349) Typically used to write TX payload, Rx/Tx address */
(0350) /**************************************************/
(0351) unsigned char SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes)
(0352) {
(0353) unsigned char status,byte_ctr;
(0354) nRF24L01_CSNL; // Set nRF24L01_CSN low, init SPI tranaction
0156 985E CBI 0x0B,6
(0355) delay();
0157 DF93 RCALL _delay
(0356) status = SPI_RW(reg); // Select register to write to and read status byte
0158 2F04 MOV R16,R20
0159 DFA9 RCALL _SPI_RW
015A 2F40 MOV R20,R16
(0357) for(byte_ctr=0; byte_ctr<bytes; byte_ctr++) // then write all byte in buffer(*pBuf)
015B 2766 CLR R22
015C C006 RJMP 0x0163
(0358) status = SPI_RW(*pBuf++);
015D 01F6 MOVW R30,R12
015E 9101 LD R16,Z+
015F 016F MOVW R12,R30
0160 DFA2 RCALL _SPI_RW
0161 2F40 MOV R20,R16
0162 9563 INC R22
0163 156A CP R22,R10
0164 F3C0 BCS 0x015D
(0359) nRF24L01_CSNH; // Set nRF24L01_CSN high again
0165 9A5E SBI 0x0B,6
(0360) delay();
0166 DF84 RCALL _delay
(0361) return(status); // return nRF24L01 status byte
0167 2F04 MOV R16,R20
0168 D071 RCALL pop_gset4
0169 9508 RET
_RX_Mode:
016A 9721 SBIW R28,1
(0362) }
(0363) /**************************************************
(0364) Function: RX_Mode();
(0365)
(0366) Description:
(0367) This function initializes one nRF24L01 device to
(0368) RX Mode, set RX address, writes RX payload width,
(0369) select RF channel, datarate & LNA HCURR.
(0370) After init, CE is toggled high, which means that
(0371) this device is now ready to receive a datapacket. */
(0372) /**************************************************/
(0373) void RX_Mode(void)
(0374) {
(0375) nRF24L01_CEL;
016B 985D CBI 0x0B,5
(0376) delay();
016C DF7E RCALL _delay
(0377) SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // Use the same address on the RX device as the TX device
016D E085 LDI R24,5
016E 8388 STD Y+0,R24
016F E420 LDI R18,0x40
0170 E031 LDI R19,1
0171 E20A LDI R16,0x2A
0172 DFDF RCALL _SPI_Write_Buf
(0378)
(0379) SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
0173 E021 LDI R18,1
0174 E201 LDI R16,0x21
0175 DFA5 RCALL _SPI_RW_Reg
(0380) SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
0176 E021 LDI R18,1
0177 E202 LDI R16,0x22
0178 DFA2 RCALL _SPI_RW_Reg
(0381) SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40
0179 E228 LDI R18,0x28
017A E205 LDI R16,0x25
017B DF9F RCALL _SPI_RW_Reg
(0382) SPI_RW_Reg(WRITE_REG + RX_PW_P0, TX_PLOAD_WIDTH); // Select same RX payload width as TX Payload width
017C E124 LDI R18,0x14
017D E301 LDI R16,0x31
017E DF9C RCALL _SPI_RW_Reg
(0383) SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
017F E027 LDI R18,7
0180 E206 LDI R16,0x26
0181 DF99 RCALL _SPI_RW_Reg
(0384) SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:RX. RX_DR enabled..
0182 E02F LDI R18,0xF
0183 E200 LDI R16,0x20
0184 DF96 RCALL _SPI_RW_Reg
(0385) nRF24L01_CEH;
0185 9A5D SBI 0x0B,5
(0386) delay();
0186 DF64 RCALL _delay
0187 9621 ADIW R28,1
0188 9508 RET
_TX_Mode:
0189 9721 SBIW R28,1
(0387) // This device is now ready to receive one packet of 16 bytes payload from a TX device sending to address
(0388) // '3443101001', with auto acknowledgment, retransmit count of 10, RF channel 40 and datarate = 2Mbps.
(0389)
(0390) }
(0391) /**************************************************/
(0392)
(0393) /**************************************************
(0394) Function: TX_Mode();
(0395)
(0396) Description:
(0397) This function initializes one nRF24L01 device to
(0398) TX mode, set TX address, set RX address for auto.ack,
(0399) fill TX payload, select RF channel, datarate & TX pwr.
(0400) PWR_UP is set, CRC(2 bytes) is enabled, & PRIM:TX.
(0401)
(0402) ToDo: One high pulse(>10us) on CE will now send this
(0403) packet and expext an acknowledgment from the RX device. */
(0404) /**************************************************/
(0405) void TX_Mode(void)
(0406) {
(0407) nRF24L01_CEL;
018A 985D CBI 0x0B,5
(0408) delay();
018B DF5F RCALL _delay
(0409) SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); // Writes TX_Address to nRF24L01
018C E085 LDI R24,5
018D 8388 STD Y+0,R24
018E E420 LDI R18,0x40
018F E031 LDI R19,1
0190 E300 LDI R16,0x30
0191 DFC0 RCALL _SPI_Write_Buf
(0410) SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH); // RX_Addr0 same as TX_Adr for Auto.Ack
0192 E085 LDI R24,5
0193 8388 STD Y+0,R24
0194 E420 LDI R18,0x40
0195 E031 LDI R19,1
0196 E20A LDI R16,0x2A
0197 DFBA RCALL _SPI_Write_Buf
(0411) SPI_Write_Buf(WR_TX_PLOAD, Buffer, TX_PLOAD_WIDTH); // Writes data to TX payload
0198 E184 LDI R24,0x14
0199 8388 STD Y+0,R24
019A E020 LDI R18,0
019B E031 LDI R19,1
019C EA00 LDI R16,0xA0
019D DFB4 RCALL _SPI_Write_Buf
(0412)
(0413) SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // Enable Auto.Ack:Pipe0
019E E021 LDI R18,1
019F E201 LDI R16,0x21
01A0 DF7A RCALL _SPI_RW_Reg
(0414) SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // Enable Pipe0
01A1 E021 LDI R18,1
01A2 E202 LDI R16,0x22
01A3 DF77 RCALL _SPI_RW_Reg
(0415) SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x1a); // 500us + 86us, 10 retrans...
01A4 E12A LDI R18,0x1A
01A5 E204 LDI R16,0x24
01A6 DF74 RCALL _SPI_RW_Reg
(0416) SPI_RW_Reg(WRITE_REG + RF_CH, 40); // Select RF channel 40
01A7 E228 LDI R18,0x28
01A8 E205 LDI R16,0x25
01A9 DF71 RCALL _SPI_RW_Reg
(0417) SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); // TX_PWR:0dBm, Datarate:2Mbps, LNA:HCURR
01AA E027 LDI R18,7
01AB E206 LDI R16,0x26
01AC DF6E RCALL _SPI_RW_Reg
(0418) SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // Set PWR_UP bit, enable CRC(2 bytes) & Prim:TX. MAX_RT & TX_DS enabled..
01AD E02E LDI R18,0xE
01AE E200 LDI R16,0x20
01AF DF6B RCALL _SPI_RW_Reg
(0419) nRF24L01_CEH;
01B0 9A5D SBI 0x0B,5
(0420) delay();
01B1 DF39 RCALL _delay
01B2 9621 ADIW R28,1
01B3 9508 RET
(0421)
(0422) }
(0423) //------------------------------------------------------
(0424) void timer0_init(void)
(0425) {
(0426) TCCR0B = 0x00; //stop
_timer0_init:
01B4 2422 CLR R2
01B5 BC25 OUT 0x25,R2
(0427) TCNT0 = 0x06; //set count
01B6 E086 LDI R24,6
01B7 BD86 OUT 0x26,R24
(0428) TCCR0A = 0x00;
01B8 BC24 OUT 0x24,R2
(0429) TCCR0B = 0x02; //start timer
01B9 E082 LDI R24,2
01BA BD85 OUT 0x25,R24
01BB 9508 RET
_timer0_ovf_isr:
01BC 922A ST R2,-Y
01BD 938A ST R24,-Y
01BE B62F IN R2,0x3F
01BF 922A ST R2,-Y
(0430) }
(0431) #pragma interrupt_handler timer0_ovf_isr:17
(0432) void timer0_ovf_isr(void) // 5ms
(0433) {
(0434)
(0435) TCNT0 = 0x06; //reload counter value
01C0 E086 LDI R24,6
01C1 BD86 OUT 0x26,R24
(0436)
(0437) if((--t20ms)==0)
01C2 9180015C LDS R24,t20ms
01C4 5081 SUBI R24,1
01C5 2E28 MOV R2,R24
01C6 9220015C STS t20ms,R2
01C8 2388 TST R24
01C9 F449 BNE 0x01D3
(0438) {
(0439) set(flag,bit20ms);
01CA 9180015B LDS R24,flag
01CC 6081 ORI R24,1
01CD 9380015B STS flag,R24
(0440) t20ms=t20msC;
01CF E580 LDI R24,0x50
01D0 9380015C STS t20ms,R24
(0441) //=================================
(0442) NOP();
01D2 0000 NOP
(0443) // if(PINB& CC1100_MISO)
(0444) //======================================
(0445) // key1_time为长按时间 KEY—TIME越大时间越长
(0446) //======================================
(0447)
(0448) //=================================
(0449) }
FILE: <library>
01D3 9029 LD R2,Y+
01D4 BE2F OUT 0x3F,R2
01D5 9189 LD R24,Y+
01D6 9029 LD R2,Y+
01D7 9518 RETI
pop_gset2:
01D8 E0E2 LDI R30,2
01D9 C00E RJMP pop
pop_gset4:
01DA E0E8 LDI R30,0x8
01DB C00C RJMP pop
push_gset5:
01DC 92FA ST R15,-Y
01DD 92EA ST R14,-Y
push_gset4:
01DE 92DA ST R13,-Y
01DF 92CA ST R12,-Y
push_gset3:
01E0 92BA ST R11,-Y
01E1 92AA ST R10,-Y
push_gset2:
01E2 937A ST R23,-Y
01E3 936A ST R22,-Y
push_gset1:
01E4 935A ST R21,-Y
01E5 934A ST R20,-Y
01E6 9508 RET
pop_gset1:
01E7 E0E1 LDI R30,1
pop:
01E8 9149 LD R20,Y+
01E9 9159 LD R21,Y+
01EA FDE0 SBRC R30,0
01EB 9508 RET
01EC 9169 LD R22,Y+
01ED 9179 LD R23,Y+
01EE FDE1 SBRC R30,1
01EF 9508 RET
01F0 90A9 LD R10,Y+
01F1 90B9 LD R11,Y+
01F2 FDE2 SBRC R30,2
01F3 9508 RET
01F4 90C9 LD R12,Y+
01F5 90D9 LD R13,Y+
01F6 FDE3 SBRC R30,3
01F7 9508 RET
01F8 90E9 LD R14,Y+
01F9 90F9 LD R15,Y+
01FA 9508 RET
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