📄 2.4g+̤
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00BD 2422 CLR R2
00BE B825 OUT 0x05,R2
(0193) // nrf24l01init();
(0194) // nRF24L01_CEL;
(0195) // delay();
(0196) // nRF24L01_CSNH; // Spi disable
(0197) // delay();
(0198) // nRF24L01_SCKL;
(0199) // delay();
(0200) // Buffer[1]=0;
(0201) RX_Mode();
00BF D0AA RCALL _RX_Mode
00C0 CFAD RJMP 0x006E
00C1 9621 ADIW R28,1
00C2 9508 RET
(0202) // delayms(1000); //延时10ms*10=100ms
(0203) }
(0204) }
(0205)
(0206)
(0207) }
(0208) void nrf24l01init(void)
(0209) {
(0210) nRF24L01_IRQ_DIR;
_nrf24l01init:
00C3 9822 CBI 0x04,2
(0211) nRF24L01_MISO_DIR;
00C4 9821 CBI 0x04,1
(0212) nRF24L01_CE_DIR;
00C5 9A55 SBI 0x0A,5
(0213) nRF24L01_SCK_DIR;
00C6 9A57 SBI 0x0A,7
(0214) nRF24L01_CSN_DIR;
00C7 9A56 SBI 0x0A,6
(0215) nRF24L01_MOSI_DIR;
00C8 9A20 SBI 0x04,0
00C9 9508 RET
(0216) }
(0217) /*-----------------------------------------------------------------------------
(0218) Module: init_CPU
(0219) Function: Initialization of CPU
(0220) ------------------------------------------------------------------------------*/
(0221) void init_CPU (void)
(0222) {
(0223) MCUCR = 0x00; //
_init_CPU:
00CA 2422 CLR R2
00CB BE25 OUT 0x35,R2
(0224) EICRA = 0x00; //extended ext ints
00CC 92200069 STS 0x69,R2
(0225) EIMSK = 0x00;
00CE BA2D OUT 0x1D,R2
(0226)
(0227) TIMSK0 = 0x01; //timer 0 interrupt sources
00CF E081 LDI R24,1
00D0 9380006E STS 0x6E,R24
(0228) TIMSK1 = 0x00; //timer 1 interrupt sources
00D2 9220006F STS 0x6F,R2
(0229) TIMSK2 = 0x00; //timer 2 interrupt sources
00D4 92200070 STS 0x70,R2
(0230) CLI(); //disable all interrupts
00D6 94F8 BCLR 7
(0231) NOP();
00D7 0000 NOP
(0232) PORTB = 0x01;
00D8 B985 OUT 0x05,R24
(0233) DDRB = 0xf3;
00D9 EF83 LDI R24,0xF3
00DA B984 OUT 0x04,R24
(0234) PORTD = 0x80;
00DB E880 LDI R24,0x80
00DC B98B OUT 0x0B,R24
(0235) DDRD = 0xff;
00DD EF8F LDI R24,0xFF
00DE B98A OUT 0x0A,R24
(0236) PORTC = 0x80;
00DF E880 LDI R24,0x80
00E0 B988 OUT 0x08,R24
(0237) DDRC = 0x78;
00E1 E788 LDI R24,0x78
00E2 B987 OUT 0x07,R24
(0238) nrf24l01init();
00E3 DFDF RCALL _nrf24l01init
(0239) nRF24L01_CEL;
00E4 985D CBI 0x0B,5
(0240) delay();
00E5 D005 RCALL _delay
(0241) nRF24L01_CSNH; // Spi disable
00E6 9A5E SBI 0x0B,6
(0242) delay();
00E7 D003 RCALL _delay
(0243) nRF24L01_SCKL;
00E8 985F CBI 0x0B,7
(0244) delay();
00E9 D001 RCALL _delay
00EA 9508 RET
(0245) }
(0246) void delay(void)//
(0247) {
(0248) NOP();
_delay:
00EB 0000 NOP
(0249) NOP();
00EC 0000 NOP
(0250) NOP();
00ED 0000 NOP
(0251) NOP();
00EE 0000 NOP
(0252) NOP();
00EF 0000 NOP
(0253) NOP();
00F0 0000 NOP
00F1 9508 RET
(0254) }
(0255) void delayms(unsigned short dly)//
(0256) {
(0257) for(;dly>0;dly--) ;
_delayms:
dly --> R16
00F2 C002 RJMP 0x00F5
00F3 5001 SUBI R16,1
00F4 4010 SBCI R17,0
00F5 3000 CPI R16,0
00F6 0701 CPC R16,R17
00F7 F7D9 BNE 0x00F3
00F8 9508 RET
(0258) }
(0259)
(0260) void clear_buf(unsigned char *ptr,unsigned char number)//清零buffer,指定字节个数
(0261) {
(0262) for (;number>0;number--) *ptr++=0;
_clear_buf:
number --> R18
ptr --> R16
00F9 C005 RJMP 0x00FF
00FA 2422 CLR R2
00FB 01F8 MOVW R30,R16
00FC 9221 ST R2,Z+
00FD 018F MOVW R16,R30
00FE 952A DEC R18
00FF 2422 CLR R2
0100 1622 CP R2,R18
0101 F3C0 BCS 0x00FA
0102 9508 RET
_SPI_RW:
bit_ctr --> R20
byte --> R22
0103 D0DE RCALL push_gset2
0104 2F60 MOV R22,R16
(0263) }
(0264) //------------------------------------------------------
(0265) /**************************************************
(0266) Function: SPI_RW();
(0267)
(0268) Description:
(0269) Writes one byte to nRF24L01, and return the byte read
(0270) from nRF24L01 during write, according to SPI protocol */
(0271) /**************************************************/
(0272) unsigned char SPI_RW(unsigned char byte)
(0273) {
(0274) unsigned char bit_ctr;
(0275) for(bit_ctr=0;bit_ctr<8;bit_ctr++) // output 8-bit
0105 2744 CLR R20
0106 C00F RJMP 0x0116
(0276) {
(0277) if(byte & 0x80)
0107 FF67 SBRS R22,7
0108 C002 RJMP 0x010B
(0278) nRF24L01_MOSIH;
0109 9A28 SBI 0x05,0
010A C001 RJMP 0x010C
(0279) else
(0280) nRF24L01_MOSIL;
010B 9828 CBI 0x05,0
(0281) delay();
010C DFDE RCALL _delay
(0282) byte = (byte << 1); // shift next bit into MSB..
010D 0F66 LSL R22
(0283) nRF24L01_SCKH;
010E 9A5F SBI 0x0B,7
(0284) delay();
010F DFDB RCALL _delay
(0285) if(PINB&nRF24L01_MISO) byte |= 1;
0110 9B19 SBIS 0x03,1
0111 C001 RJMP 0x0113
0112 6061 ORI R22,1
(0286) nRF24L01_SCKL;
0113 985F CBI 0x0B,7
(0287) delay();
0114 DFD6 RCALL _delay
0115 9543 INC R20
0116 3048 CPI R20,0x8
0117 F378 BCS 0x0107
(0288) }
(0289) return(byte); // return read byte
0118 2F06 MOV R16,R22
0119 D0BE RCALL pop_gset2
011A 9508 RET
_SPI_RW_Reg:
status --> R20
value --> R22
reg --> R20
011B D0C6 RCALL push_gset2
011C 2F62 MOV R22,R18
011D 2F40 MOV R20,R16
(0290) }
(0291) /**************************************************
(0292) Function: SPI_RW_Reg();
(0293)
(0294) Description:
(0295) Writes value 'value' to register 'reg' */
(0296) /**************************************************/
(0297) unsigned char SPI_RW_Reg(unsigned char reg, unsigned char value)
(0298) {
(0299) unsigned char status;
(0300) nRF24L01_CSNL;
011E 985E CBI 0x0B,6
(0301) delay();
011F DFCB RCALL _delay
(0302) status = SPI_RW(reg); // select register
0120 2F04 MOV R16,R20
0121 DFE1 RCALL _SPI_RW
0122 2F40 MOV R20,R16
(0303) SPI_RW(value); // ..and write value to it..
0123 2F06 MOV R16,R22
0124 DFDE RCALL _SPI_RW
(0304) nRF24L01_CSNH;
0125 9A5E SBI 0x0B,6
(0305) delay();
0126 DFC4 RCALL _delay
(0306) return(status); // return nRF24L01 status byte
0127 2F04 MOV R16,R20
0128 D0AF RCALL pop_gset2
0129 9508 RET
_SPI_Read:
reg_val --> R20
reg --> R20
012A D0B9 RCALL push_gset1
012B 2F40 MOV R20,R16
(0307) }
(0308) /**************************************************
(0309) Function: SPI_Read();
(0310)
(0311) Description:
(0312) Read one byte from nRF24L01 register, 'reg' */
(0313) /**************************************************/
(0314) unsigned char SPI_Read(unsigned char reg)
(0315) {
(0316) unsigned char reg_val;
(0317) nRF24L01_CSNL;
012C 985E CBI 0x0B,6
(0318) delay();
012D DFBD RCALL _delay
(0319) SPI_RW(reg); // Select register to read from..
012E 2F04 MOV R16,R20
012F DFD3 RCALL _SPI_RW
(0320) reg_val = SPI_RW(0); // ..then read registervalue
0130 2700 CLR R16
0131 DFD1 RCALL _SPI_RW
0132 2F40 MOV R20,R16
(0321) nRF24L01_CSNH;
0133 9A5E SBI 0x0B,6
(0322) delay();
0134 DFB6 RCALL _delay
(0323) return(reg_val); // return register value
0135 2F04 MOV R16,R20
0136 D0B0 RCALL pop_gset1
0137 9508 RET
_SPI_Read_Buf:
status --> R20
byte_ctr --> R22
bytes --> R10
pBuf --> R12
reg --> R20
0138 D0A5 RCALL push_gset4
0139 0169 MOVW R12,R18
013A 2F40 MOV R20,R16
013B 84A8 LDD R10,Y+8
(0324) }
(0325) /**************************************************
(0326) Function: SPI_Read_Buf();
(0327)
(0328) Description:
(0329) Reads 'bytes' #of bytes from register 'reg'
(0330) Typically used to read RX payload, Rx/Tx address */
(0331) /**************************************************/
(0332) unsigned char SPI_Read_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes)
(0333) {
(0334) unsigned char status,byte_ctr;
(0335) nRF24L01_CSNL;
013C 985E CBI 0x0B,6
(0336) delay();
013D DFAD RCALL _delay
(0337) status = SPI_RW(reg); // Select register to write to and read status byte
013E 2F04 MOV R16,R20
013F DFC3 RCALL _SPI_RW
0140 2F40 MOV R20,R16
(0338) for(byte_ctr=0;byte_ctr<bytes;byte_ctr++)
0141 2766 CLR R22
0142 C008 RJMP 0x014B
(0339) pBuf[byte_ctr] = SPI_RW(0); // Perform SPI_RW to read byte from nRF24L01
0143 2700 CLR R16
0144 DFBE RCALL _SPI_RW
0145 2FE6 MOV R30,R22
0146 27FF CLR R31
0147 0DEC ADD R30,R12
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