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.module main.c
.area data(ram, con, rel)
0000 _Buffer::
0000 .blkb 2
.area idata
0000 0000 .byte 0,0
.area data(ram, con, rel)
0002 .blkb 2
.area idata
0002 0000 .byte 0,0
.area data(ram, con, rel)
0004 .blkb 2
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0004 0000 .byte 0,0
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0006 .blkb 2
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0006 0000 .byte 0,0
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0008 .blkb 2
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0008 0000 .byte 0,0
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000A .blkb 2
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000A 0000 .byte 0,0
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000C .blkb 2
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000C 0000 .byte 0,0
.area data(ram, con, rel)
000E .blkb 2
.area idata
000E 0000 .byte 0,0
.area data(ram, con, rel)
0010 .blkb 2
.area idata
0010 0000 .byte 0,0
.area data(ram, con, rel)
0012 .blkb 2
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0012 0000 .byte 0,0
.area data(ram, con, rel)
0014 .blkb 2
.area idata
0014 0000 .byte 0,0
.area data(ram, con, rel)
0016 .blkb 2
.area idata
0016 0000 .byte 0,0
.area data(ram, con, rel)
0018 .blkb 2
.area idata
0018 0000 .byte 0,0
.area data(ram, con, rel)
001A .blkb 2
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001A 0000 .byte 0,0
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001C .blkb 2
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001C 0000 .byte 0,0
.area data(ram, con, rel)
001E .blkb 2
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001E 0000 .byte 0,0
.area data(ram, con, rel)
0020 .blkb 2
.area idata
0020 0000 .byte 0,0
.area data(ram, con, rel)
0022 .blkb 2
.area idata
0022 0000 .byte 0,0
.area data(ram, con, rel)
0024 .blkb 2
.area idata
0024 0000 .byte 0,0
.area data(ram, con, rel)
0026 .blkb 2
.area idata
0026 0000 .byte 0,0
.area data(ram, con, rel)
0028 .blkb 2
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0028 0000 .byte 0,0
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002A .blkb 2
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002A 0000 .byte 0,0
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002C .blkb 2
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002C 0000 .byte 0,0
.area data(ram, con, rel)
002E .blkb 2
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002E 0000 .byte 0,0
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0030 .blkb 2
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0030 0000 .byte 0,0
.area data(ram, con, rel)
0032 .blkb 2
.area idata
0032 0000 .byte 0,0
.area data(ram, con, rel)
0034 .blkb 2
.area idata
0034 0000 .byte 0,0
.area data(ram, con, rel)
0036 .blkb 2
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0036 0000 .byte 0,0
.area data(ram, con, rel)
0038 .blkb 2
.area idata
0038 0000 .byte 0,0
.area data(ram, con, rel)
003A .blkb 2
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003A 0000 .byte 0,0
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003C .blkb 2
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003C 0000 .byte 0,0
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003E .blkb 2
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003E 0000 .byte 0,0
.area data(ram, con, rel)
0040 .dbfile E:\项目\PS2无~1\progamme\acceptavrnrf24l01\acceptavrnrf24l01\main.c
0040 .dbsym e Buffer _Buffer A[64:64]c
0040 _TX_ADDRESS::
0040 .blkb 2
.area idata
0040 3443 .byte 52,'C
.area data(ram, con, rel)
0042 .dbfile E:\项目\PS2无~1\progamme\acceptavrnrf24l01\acceptavrnrf24l01\main.c
0042 .blkb 2
.area idata
0042 1010 .byte 16,16
.area data(ram, con, rel)
0044 .dbfile E:\项目\PS2无~1\progamme\acceptavrnrf24l01\acceptavrnrf24l01\main.c
0044 .blkb 1
.area idata
0044 01 .byte 1
.area data(ram, con, rel)
0045 .dbfile E:\项目\PS2无~1\progamme\acceptavrnrf24l01\acceptavrnrf24l01\main.c
0045 .dbsym e TX_ADDRESS _TX_ADDRESS A[5:5]c
0045 _accept_flag::
0045 .blkb 1
.area idata
0045 00 .byte 0
.area data(ram, con, rel)
0046 .dbfile E:\项目\PS2无~1\progamme\acceptavrnrf24l01\acceptavrnrf24l01\main.c
0046 .dbsym e accept_flag _accept_flag c
0046 _send_flag::
0046 .blkb 1
.area idata
0046 00 .byte 0
.area data(ram, con, rel)
0047 .dbfile E:\项目\PS2无~1\progamme\acceptavrnrf24l01\acceptavrnrf24l01\main.c
0047 .dbsym e send_flag _send_flag c
0047 _accept_time::
0047 .blkb 2
.area idata
0047 0000 .word 0
.area data(ram, con, rel)
0049 .dbfile E:\项目\PS2无~1\progamme\acceptavrnrf24l01\acceptavrnrf24l01\main.c
0049 .dbsym e accept_time _accept_time i
.area text(rom, con, rel)
0000 .dbfile E:\项目\PS2无~1\progamme\acceptavrnrf24l01\acceptavrnrf24l01\main.c
0000 .dbfunc e main _main fV
0000 ; Get_SO -> R20
.even
0000 _main::
0000 2197 sbiw R28,1
0002 .dbline -1
0002 .dbline 149
0002 ; //ICC-AVR application builder : 2006-02-12 14:00:00
0002 ; // Target : ATmega48
0002 ; // Crystal: 8.000Mhz
0002 ; // Author: jackyan
0002 ; // Oled Type : white
0002 ; //#define fosc 8000000
0002 ; //#define baud 9600
0002 ; #include "iom48v.h"
0002 ; #include "macros.h"
0002 ; #include "defs.h"
0002 ; /*-----------------------------------------------------------------------------
0002 ; Global Defines
0002 ; ------------------------------------------------------------------------------*/
0002 ; unsigned char key_debug;
0002 ; unsigned char Buffer[]={
0002 ; 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
0002 ; 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
0002 ; 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
0002 ; 0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,0X00,
0002 ; };
0002 ; #define TX_ADR_WIDTH 5 // 5 bytes TX(RX) address width
0002 ; #define TX_PLOAD_WIDTH 20 // 16 bytes TX payload
0002 ; unsigned char TX_ADDRESS[TX_ADR_WIDTH] = {0x34,0x43,0x10,0x10,0x01}; // Define a static TX address
0002 ; void init_CPU (void);
0002 ; void delayms(unsigned short dly);//当dly=1时，延时的时间是1ms 4MHz晶震
0002 ; void INIT_io(void);
0002 ; void RX_Mode(void);
0002 ; void TX_Mode(void);
0002 ; void delay(void);
0002 ; unsigned char SPI_Write_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
0002 ; unsigned char SPI_Read_Buf(unsigned char reg, unsigned char *pBuf, unsigned char bytes);
0002 ; unsigned char SPI_RW_Reg(unsigned char reg, unsigned char value);
0002 ; unsigned char SPI_Read(unsigned char reg);
0002 ; void clear_buf(unsigned char *ptr,unsigned char number);
0002 ; unsigned char accept_flag=0;
0002 ; unsigned char send_flag=0;
0002 ; unsigned int accept_time=0;
0002 ; void nrf24l01init(void);
0002 ; //****************************************************************//
0002 ; // SPI(nRF24L01) commands
0002 ; #define READ_REG 0x00 // Define read command to register
0002 ; #define WRITE_REG 0x20 // Define write command to register
0002 ; #define RD_RX_PLOAD 0x61 // Define RX payload register address
0002 ; #define WR_TX_PLOAD 0xA0 // Define TX payload register address
0002 ; #define FLUSH_TX 0xE1 // Define flush TX register command
0002 ; #define FLUSH_RX 0xE2 // Define flush RX register command
0002 ; #define REUSE_TX_PL 0xE3 // Define reuse TX payload register command
0002 ; //#define NOP 0xFF // Define No Operation, might be used to read status register
0002 ; //***************************************************//
0002 ; // SPI(nRF24L01) registers(addresses)
0002 ; #define CONFIG 0x00 // 'Config' register address
0002 ; #define EN_AA 0x01 // 'Enable Auto Acknowledgment' register address
0002 ; #define EN_RXADDR 0x02 // 'Enabled RX addresses' register address
0002 ; #define SETUP_AW 0x03 // 'Setup address width' register address
0002 ; #define SETUP_RETR 0x04 // 'Setup Auto. Retrans' register address
0002 ; #define RF_CH 0x05 // 'RF channel' register address
0002 ; #define RF_SETUP 0x06 // 'RF setup' register address
0002 ; #define STATUS 0x07 // 'Status' register address
0002 ; #define OBSERVE_TX 0x08 // 'Observe TX' register address
0002 ; #define CD 0x09 // 'Carrier Detect' register address
0002 ; #define RX_ADDR_P0 0x0A // 'RX address pipe0' register address
0002 ; #define RX_ADDR_P1 0x0B // 'RX address pipe1' register address
0002 ; #define RX_ADDR_P2 0x0C // 'RX address pipe2' register address
0002 ; #define RX_ADDR_P3 0x0D // 'RX address pipe3' register address
0002 ; #define RX_ADDR_P4 0x0E // 'RX address pipe4' register address
0002 ; #define RX_ADDR_P5 0x0F // 'RX address pipe5' register address
0002 ; #define TX_ADDR 0x10 // 'TX address' register address
0002 ; #define RX_PW_P0 0x11 // 'RX payload width, pipe0' register address
0002 ; #define RX_PW_P1 0x12 // 'RX payload width, pipe1' register address
0002 ; #define RX_PW_P2 0x13 // 'RX payload width, pipe2' register address
0002 ; #define RX_PW_P3 0x14 // 'RX payload width, pipe3' register address
0002 ; #define RX_PW_P4 0x15 // 'RX payload width, pipe4' register address
0002 ; #define RX_PW_P5 0x16 // 'RX payload width, pipe5' register address
0002 ; #define FIFO_STATUS 0x17 // 'FIFO Status Register' register address
0002 ; #define MAX_RT 0x10 // Max #of TX retrans interrupt
0002 ; #define TX_DS 0x20 // TX data sent interrupt
0002 ; #define RX_DR 0x40 // RX data received
0002 ; //-----------------------------------------------------------------------------
0002 ; //------------------------------------------------------
0002 ; unsigned char t20ms;
0002 ; #define BIT(x) (1 << (x))
0002 ; #define SETBIT(x, y) (x |= y)
0002 ; #define CLEARBIT(x, y) (x &= ~y)
0002 ; #define CHECKBIT(x, y) (x & y)
0002 ; #define BIT7 0x80
0002 ; #define BIT6 0x40
0002 ; #define BIT5 0x20
0002 ; #define BIT4 0x10
0002 ; #define BIT3 0x08
0002 ; #define BIT2 0x04
0002 ; #define BIT1 0x02
0002 ; #define BIT0 0x01
0002 ; #define nRF24L01_CSN BIT6
0002 ; #define nRF24L01_SCK BIT7
0002 ; #define nRF24L01_MOSI BIT0
0002 ; #define nRF24L01_CE BIT5
0002 ; #define nRF24L01_MISO BIT1
0002 ; #define nRF24L01_IRQ BIT2
0002 ; #define nRF24L01_CSNH SETBIT(PORTD, nRF24L01_CSN)
0002 ; #define nRF24L01_CSNL CLEARBIT(PORTD, nRF24L01_CSN)
0002 ;
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