📄 test_nandflash.v
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module TEST_NANDFLASH
(
//HSPI Output Signals
clk,
rst_n,
ctrl,
wr_n,
NFL_CLE,
NFL_ALE,
NFL_nCE,
NFL_nWE,
NFL_nRE,
NFL_DATA,
ID
);
//Outputs
input clk,rst_n;
input wr_n;
input [3:0] ctrl;
output NFL_CLE,NFL_ALE,NFL_nCE,NFL_nWE,NFL_nRE;
inout [7:0] NFL_DATA;
reg [7:0] NFL_DATA_OUT;
output [31:0] ID;
//Signal Declarations
reg NF_CLE,NF_ALE,NF_nCE,NF_nWE,NF_nRE;
reg NFL_CLE,NFL_ALE,NFL_nCE,NFL_nWE,NFL_nRE;
//NAND FLASH
reg [7:0] NANDFLASHID0,NANDFLASHID1,NANDFLASHID2,NANDFLASHID3;
//NAND FLAH ORD
parameter NFLASH_READID_CMD = 8'h90;
parameter NFLASH_READID_ADDR = 8'h00;
wire nf_ord_read1 = (!ctrl[3] & !ctrl[2] & !ctrl[1] & !ctrl[0]) & !wr_n;//0000
wire nf_ord_read2 = (!ctrl[3] & !ctrl[2] & !ctrl[1] & ctrl[0]) & !wr_n;//0001
wire nf_ord_readid = (!ctrl[3] & !ctrl[2] & ctrl[1] & !ctrl[0]) & !wr_n;//0010
wire nf_ord_reset = (!ctrl[3] & !ctrl[2] & ctrl[1] & ctrl[0]) & !wr_n;//0011
wire nf_ord_pageprogram = (!ctrl[3] & ctrl[2] & !ctrl[1] & !ctrl[0]) & !wr_n;//0100
wire nf_ord_blockerase = (!ctrl[3] & ctrl[2] & !ctrl[1] & ctrl[0]) & !wr_n;//0101
wire nf_ord_blockprotect1 = (!ctrl[3] & ctrl[2] & ctrl[1] & !ctrl[0]) & !wr_n;//0110
wire nf_ord_blockprotect2 = (!ctrl[3] & ctrl[2] & ctrl[1] & ctrl[0]) & !wr_n;//0111
wire nf_ord_blockprotect3 = (ctrl[3] & !ctrl[2] & !ctrl[1] & !ctrl[0]) & !wr_n;//1000
wire nf_ord_readstatus = (ctrl[3] & !ctrl[2] & !ctrl[1] & ctrl[0]) & !wr_n;//1001
wire nf_ord_readprotectionstate = (ctrl[3] & !ctrl[2] & ctrl[1] & !ctrl[0]) & !wr_n;//1010
assign ID = {NANDFLASHID0,NANDFLASHID1,NANDFLASHID2,NANDFLASHID3};
always@(posedge clk)
begin
NFL_CLE <= NF_CLE;
NFL_ALE <= NF_ALE;
NFL_nCE <= NF_nCE;
NFL_nWE <= NF_nWE;
NFL_nRE <= NF_nRE;
end
//Delay FSM----------------------------------------------------------------------//
reg [1:0] DF_state;
reg [2:0] delayCNT;
reg [2:0] delay_maxCNT;
reg LoadDFcnt;
reg incDFcnt;
reg delay_ok;
always@(posedge clk )
begin
if (LoadDFcnt == 1'b1) begin
delayCNT <= delay_maxCNT;
delay_ok <= 1'b0;
end else
if (delayCNT > 0 ) begin
delayCNT <= delayCNT - 1;
delay_ok <= 1'b0;
end else if (delayCNT == 0 )begin
delayCNT <= 0;
delay_ok <= 1'b1;
end
end
//addr repeat
reg [2:0] repeat_addr_CNT;
reg [2:0] repeat_addr_maxCNT;
reg LoadRPcnt_addr;
reg incRPcnt_addr;
reg repeat_addr_ok;
reg repeat_addr_en;
always@( negedge clk )
begin
if (LoadRPcnt_addr == 1'b1) begin
repeat_addr_CNT <= repeat_addr_maxCNT;
repeat_addr_ok <= 1'b0;
end else if (repeat_addr_CNT == 0 )begin
repeat_addr_CNT <= 0;
repeat_addr_ok <= 1'b1;
end else
if ((repeat_addr_CNT > 0) &&(repeat_addr_en == 1'b1) ) begin
repeat_addr_CNT <= repeat_addr_CNT - 1;
repeat_addr_ok <= 1'b0;
end
end
//read data repeat
reg [2:0] repeat_rdata_CNT;
reg [2:0] repeat_rdata_maxCNT;
reg LoadRPcnt_rdata;
reg incRPcnt_rdata;
reg repeat_rdata_ok;
reg repeat_rdata_en;
always@( negedge clk )
begin
if (LoadRPcnt_rdata == 1'b1) begin
repeat_rdata_CNT <= repeat_rdata_maxCNT;
repeat_rdata_ok <= 1'b0;
end else if (repeat_rdata_CNT == 0 )begin
repeat_rdata_CNT <= 0;
repeat_rdata_ok <= 1'b1;
end else
if ((repeat_rdata_CNT > 0) && (repeat_rdata_en == 1'b1) ) begin
repeat_rdata_CNT <= repeat_rdata_CNT - 1;
repeat_rdata_ok <= 1'b0;
end
end
//DATA Write
assign NFL_DATA = NFL_nWE ? 8'hzz : NFL_DATA_OUT;
always@(negedge clk)
begin
if (!NFL_nWE) begin
if (NFL_CLE == 1'b1) NFL_DATA_OUT <= 8'h90;
else if (NFL_ALE == 1'b1) begin
NFL_DATA_OUT <= 8'h00;
end
else begin
NFL_DATA_OUT <= 8'hzz;
end
end
end
//DATA READ
always@(posedge NFL_nRE)
begin
if (repeat_rdata_CNT == 3) NANDFLASHID0 <= NFL_DATA;
else if (repeat_rdata_CNT == 2) NANDFLASHID1 <= NFL_DATA;
else if (repeat_rdata_CNT == 1) NANDFLASHID2 <= NFL_DATA;
else NANDFLASHID3 <= NFL_DATA;
end
//------------------------------------------------------------------------------//
parameter OP_IDLE = 0,
OP_START = 1,
OP_CLE = 2,
OP_WRITE_CLE = 3,
OP_NULL0 = 4,
OP_ALE = 5,
OP_WRITE_ALE_L = 6,
OP_WRITE_ALE_H = 7,
OP_NULL1 = 8,
OP_READ_DATA_L = 9,
OP_READ_DATA_H = 10;
reg [7:0] OP_STATE;
always@(negedge clk)
begin
if (nf_ord_readid == 1'b1) begin
OP_STATE <= OP_START;
//addr
repeat_addr_maxCNT <= 0;
LoadRPcnt_addr <= 1'b1;
//data
repeat_rdata_maxCNT <= 3;
LoadRPcnt_rdata <= 1;
end
else begin
LoadRPcnt_addr <= 1'b0;
LoadRPcnt_rdata <= 1'b0;
case (OP_STATE)
OP_IDLE:begin
OP_STATE <= OP_IDLE;
end
OP_START:begin
OP_STATE <= OP_CLE;
delay_maxCNT <= 2;
LoadDFcnt <= 1;
end
OP_CLE:begin
LoadDFcnt <= 0;
if (delay_ok == 1'b1) OP_STATE <= OP_WRITE_CLE;
else OP_STATE <= OP_CLE;
end
OP_WRITE_CLE:begin
OP_STATE <= OP_NULL0;
end
OP_NULL0:begin
OP_STATE <= OP_ALE;
end
OP_ALE:begin
OP_STATE <= OP_WRITE_ALE_L;
delay_maxCNT <= 1;
LoadDFcnt <= 1;
end
OP_WRITE_ALE_L:begin
repeat_addr_en = 1'b0;
LoadDFcnt <= 0;
if (delay_ok == 1'b1) begin
OP_STATE <= OP_WRITE_ALE_H;
end else
begin
OP_STATE <= OP_WRITE_ALE_L;
end
end
OP_WRITE_ALE_H:begin
repeat_addr_en = 1'b1;
if (repeat_addr_ok == 1'b1) begin
OP_STATE <= OP_NULL1;
end else
begin
OP_STATE <= OP_WRITE_ALE_L;
delay_maxCNT <= 1;
LoadDFcnt <= 1;
end
end
OP_NULL1:begin
repeat_addr_en = 1'b0;
OP_STATE <= OP_READ_DATA_L;
delay_maxCNT <= 1;
LoadDFcnt <= 1;
end
OP_READ_DATA_L:begin
repeat_rdata_en = 1'b0;
LoadDFcnt <= 0;
if (delay_ok == 1'b1) begin
OP_STATE <= OP_READ_DATA_H;
end else
begin
OP_STATE <= OP_READ_DATA_L;
end
end
OP_READ_DATA_H:begin
repeat_rdata_en = 1'b1;
if (repeat_rdata_ok == 1'b1) begin
OP_STATE <= OP_IDLE;
end else
begin
OP_STATE <= OP_READ_DATA_L;
delay_maxCNT <= 1;
LoadDFcnt <= 1;
end
end
default:OP_STATE <= OP_IDLE;
endcase
end
end
always@(OP_STATE)
begin
case(OP_STATE)
OP_IDLE:begin
NF_CLE <= 1'b0;
NF_ALE <= 1'b0;
NF_nCE <= 1'b1;
NF_nWE <= 1'b1;
NF_nRE <= 1'b1;
end
OP_START:begin
NF_CLE <= 1'b0;
NF_ALE <= 1'b0;
NF_nCE <= 1'b0;
NF_nWE <= 1'b1;
NF_nRE <= 1'b1;
end
OP_CLE:begin
NF_CLE <= 1'b1;
NF_ALE <= 1'b0;
NF_nCE <= 1'b0;
NF_nWE <= 1'b0;
NF_nRE <= 1'b1;
end
OP_WRITE_CLE:begin
NF_CLE <= 1'b1;
NF_ALE <= 1'b0;
NF_nCE <= 1'b0;
NF_nWE <= 1'b1;
NF_nRE <= 1'b1;
end
OP_NULL0:begin
NF_CLE <= 1'b0;
NF_ALE <= 1'b0;
NF_nCE <= 1'b0;
NF_nWE <= 1'b1;
NF_nRE <= 1'b1;
end
OP_ALE:begin
NF_CLE <= 1'b0;
NF_ALE <= 1'b1;
NF_nCE <= 1'b0;
NF_nWE <= 1'b1;
NF_nRE <= 1'b1;
end
OP_WRITE_ALE_L:begin
NF_CLE <= 1'b0;
NF_ALE <= 1'b1;
NF_nCE <= 1'b0;
NF_nWE <= 1'b0;
NF_nRE <= 1'b1;
end
OP_WRITE_ALE_H:begin
NF_CLE <= 1'b0;
NF_ALE <= 1'b1;
NF_nCE <= 1'b0;
NF_nWE <= 1'b1;
NF_nRE <= 1'b1;
end
OP_NULL1:begin
NF_CLE <= 1'b0;
NF_ALE <= 1'b0;
NF_nCE <= 1'b0;
NF_nWE <= 1'b1;
NF_nRE <= 1'b1;
end
OP_READ_DATA_L:begin
NF_CLE <= 1'b0;
NF_ALE <= 1'b0;
NF_nCE <= 1'b0;
NF_nWE <= 1'b1;
NF_nRE <= 1'b0;
end
OP_READ_DATA_H:begin
NF_CLE <= 1'b0;
NF_ALE <= 1'b0;
NF_nCE <= 1'b0;
NF_nWE <= 1'b1;
NF_nRE <= 1'b1;
end
default:begin
NF_CLE <= 1'b0;
NF_ALE <= 1'b0;
NF_nCE <= 1'b1;
NF_nWE <= 1'b1;
NF_nRE <= 1'b1;
end
endcase
end
endmodule
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