📄 boot.asm
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sub #'0' ; adjust first by subtracting '0'
cmp #9 ; check if value was between '0' to '9'
bls ToHex1 ; exit if so
sub #7 ; else, adjust for value between 'A' to 'F'
ToHex1:
rts ; return
;* IsHex Subroutine =======================================================================
;*
;* This subroutine checks if the value passed in ACC is a valid ASCII hex character within
;* within the ranges of '0' to '9' or 'A' to 'F'. Note that the range 'a' to 'f' is not
;* checked.
;*
;* Calling convention:
;*
;* lda data
;* jsr IsHex
;*
;* Returns: CCRZ= 1 if data is a valid hex character. Otherwise, CCRZ= 0.
;*
;* Changes: nothing
;*
IsHex:
cmp #'0' ; check value against '0'
blo IsntHex ; not hex if lower
cmp #'9' ; check value against '9'
bls IsHex1 ; is hex if lower
cmp #'A' ; check value against 'A'
blo IsntHex ; not hex if lower
cmp #'F' ; check value against 'F'
bhi IsntHex ; not hex if higher
IsHex1:
bit #0 ; CCRZ= 1
IsntHex:
rts ; return
;* Flash Mass Erase Subroutine ============================================================
;*
;* This subroutine performs multiple Page Erase operations in order to erase the application
;* space Flash memory between "flash_first" and "flash_last". This subroutine has been
;* tuned for a bus speed of 7.3728 MHz.
;* This subroutine is copied into and executed from RAM.
;*
MassErase:
ldhx flash_last ; initialize pointer to last Flash memory address
bra MassErase2 ; go move pointer before erasing Flash
MassErase1:
;
; Set ERASE, read the Flash Block Protect Register and write any data into Flash page.
;
lda #{ERASE} ; set ERASE control bit
sta flcr ; in Flash Control Register
lda flbpr ; read from Flash Block Protect Register
sta ,x ; write any data to address within page
;
; Wait for >10us, then set HVEN.
;
lda #1 ; wait
bsr delay ; for 11.7us
lda #{ERASE | HVEN} ; set HVEN control bit
sta flcr ; in Flash Control Register
;
; Wait for >1ms, then clear ERASE.
;
lda #100 ; wait
bsr delay ; for 1.005ms
lda #{HVEN} ; clear ERASE control bit
sta flcr ; in Flash Control Register
;
; Wait for >5us, then clear HVEN.
;
lda #1 ; wait
bsr delay ; for 11.7us
clra ; clear HVEN control bit
sta flcr ; in Flash Control Register
;
; Advance pointer and repeat until finished.
;
MassErase2:
aix #-64 ; move pointer back
aix #-64 ; by one complete erase page
cphx flash_first ; check if finished
bhi MassErase1 ; loop back if not
;
rts ; return
;* Delay Subroutine =======================================================================
;*
;* This subroutine performs a simple software delay loop based upon the value passed in ACC.
;* The following timing calculation applies:
;*
;* delay = ((ACC * 74) + 12) (tcyc)
;*
;* Calling convention:
;*
;* lda data
;* jsr delay
;*
;* Returns: nothing
;*
;* Changes: ACC
;*
Delay:
psha ; [2] save outer delay loop parameter
Delay1:
lda #22 ; [2] initialize inner delay loop counter
Delay2:
dbnza Delay2 ; [3] decrement inner delay loop counter
dbnz 1,sp,Delay1 ; [6] decrement outer delay loop counter
pula ; [2] deallocate local variable
rts ; [4] return
EraseRamSize: equ {*-MassErase}
ProgramRam: equ {*-Delay}
;* Flash Program Subroutine ===============================================================
;*
;* This subroutine controls the Flash programming sequence. A stack frame data block is
;* passed to it in the format shown below. This subroutine has been tuned for a bus speed
;* of 7.3728 MHz.
;* This subroutine is copied into and executed from RAM.
;*
;* | | <-sp (when called)
;* | ReturnAddr msb |
;* | ReturnAddr lsb | <-sp (upon return)
;* | SRecSize |
;* | SRecAddr msb |
;* | SRecAddr lsb |
;* | SRecData 00 |
;* | SRecData 01 | etc..
;*
FlashProgram:
tsx ; get the Stack Pointer
sthx temp_sp ; save it temporarily
;
; Get S-Record size and use the Stack Pointer as the data source pointer.
;
ais #2 ; SP points to SRecSize
pula ; get SRecSize
sta count ; save it temporarily
;
; Establish H:X as the destination pointer.
;
pulh ; get destination address msb
pulx ; get destination address lsb
FlashProgram1:
cphx flash_first ; check against minimum address
blo FlashProgram2 ; skip if lower
cphx flash_last ; check against maximum address
bhs FlashProgram2 ; skip if the same or higher
;
; Set PGM, read the Flash Block Protect Register and write anywhere in desired Flash row.
;
lda #{PGM} ; set PGM control bit
sta flcr ; in Flash Control Register
lda flbpr ; read from Flash Block Protect Register
sta ,x ; write any data to first Flash address
;
; Wait for >10us, then set HVEN.
;
lda #1 ; wait
bsr delay ; for 11.7us
lda #{PGM | HVEN} ; set HVEN control bit
sta flcr ; in Flash Control Register
;
; Wait for >5us.
;
lda #1 ; wait
bsr delay ; for 11.7us
;
; Write data to Flash and wait for 30 - 40us.
;
pula ; get S-Record data
sta ,x ; write data to Flash
lda #3 ; wait
bsr delay ; for 31.7us
;
; Clear PGM.
;
lda #{HVEN} ; clear PGM
sta flcr ; in Flash Control Register
;
; Wait for >5us, then clear HVEN.
;
lda #1 ; wait
bsr delay ; for 11.7us
clra ; clear HVEN control bit
sta flcr ; in Flash Control Register
;
; Advance destination pointer and data counter.
;
FlashProgram2:
aix #1 ; advance destination pointer
dbnz count,FlashProgram1 ; decrement counter and loop back if not done.
;
ldhx temp_sp ; restore
txs ; Stack Pointer
rts ; return
ProgramRamSize: equ {*-Delay}
;* Messages ===================================================================================
;*
ascii_CR: equ $0D ; ASCII carriage return
ascii_LF: equ $0A ; ASCII line feed
;
msg_hello: db ascii_CR,ascii_LF,'Boot>',0
msg_help: db ' (P)rogram (W)ipe (U)pgrade e(X)it',0
;
msg_complete: db ' Complete',0
msg_waiting: db ' - waiting ...',0
msg_error: db ' - error',0
msg_what: db ' - what?',0
msg_noreset: db ' - Reset Vector Invalid',0
;
; Last location not to exceed $FDFF
;
BootEnd:
;* Vectors ************************************************************************************
;*
org vec_timebase ; Timebase vector
dw user_timebase
org vec_adc ; ADC vector
dw user_ADC
org vec_kbd ; Keyboard vector
dw user_keyboard
org vec_scitx ; SCI transmit vector
dw user_SCItx
org vec_scirx ; SCI receive vector
dw user_SCIrx
org vec_scierr ; SCI error vector
dw user_SCIerr
org vec_spitx ; SPI transmit vector
dw user_SPItx
org vec_spirx ; SPI receive vector
dw user_SPIrx
org vec_tim2ov ; Timer 2 overflow vector
dw user_Tim2Ov
org vec_tim2ch1 ; Timer 2 channel 1 vector
dw user_Tim2Ch1
org vec_tim2ch0 ; Timer 2 channel 0 vector
dw user_Tim2Ch0
org vec_tim1ov ; Timer 1 oveflow vector
dw user_Tim1Ov
org vec_tim1ch1 ; Timer 1 channel 1 vector
dw user_Tim1Ch1
org vec_tim1ch0 ; Timer 1 channel 0 vector
dw user_Tim1Ch0
org vec_pll ; PLL vector
dw user_PLL
org vec_irq ; IRQ vector
dw user_IRQ
org vec_swi ; SWI vector
dw user_SWI
org vec_reset ; Reset vector
dw BootReset
;* Flash Block Protect Register ***************************************************************
;*
org flbpr
db flash_protect
end
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