erc32.c

leon2的指令模拟器。leon是应用于航天领域的一款高可靠性的sparc v7指令集的处理器。

	event(uarta_tx, 0, UART_TX_TIME);
    }
    mec_irq(4);
}

static void
uartb_tx()
{
    while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
    if (uart_stat_reg & UARTB_HRE) {
	uart_stat_reg |= UARTB_SRE;
    } else {
	uartb_sreg = uartb_hreg;
	uart_stat_reg |= UARTB_HRE;
	event(uartb_tx, 0, UART_TX_TIME);
    }
    mec_irq(5);
}

static void
uart_rx(arg)
    caddr_t         arg;
{
    int32           rsize;
    char            rxd;


    rsize = 0;
    if (f1open)
        rsize = DO_STDIO_READ(ifd1, &rxd, 1);
    if (rsize > 0) {
	uarta_data = UART_DR | rxd;
	if (uart_stat_reg & UARTA_HRE)
	    uarta_data |= UART_THE;
	if (uart_stat_reg & UARTA_SRE)
	    uarta_data |= UART_TSE;
	if (uart_stat_reg & UARTA_DR) {
	    uart_stat_reg |= UARTA_OR;
	    mec_irq(7);		/* UART error interrupt */
	}
	uart_stat_reg |= UARTA_DR;
	mec_irq(4);
    }
    rsize = 0;
    if (f2open)
        rsize = DO_STDIO_READ(ifd2, &rxd, 1);
    if (rsize) {
	uartb_data = UART_DR | rxd;
	if (uart_stat_reg & UARTB_HRE)
	    uartb_data |= UART_THE;
	if (uart_stat_reg & UARTB_SRE)
	    uartb_data |= UART_TSE;
	if (uart_stat_reg & UARTB_DR) {
	    uart_stat_reg |= UARTB_OR;
	    mec_irq(7);		/* UART error interrupt */
	}
	uart_stat_reg |= UARTB_DR;
	mec_irq(5);
    }
    event(uart_rx, 0, UART_RX_TIME);
}

static void
uart_intr(arg)
    caddr_t         arg;
{
    read_uart(0xE8);		/* Check for UART interrupts every 1000 clk */
    flush_uart();		/* Flush UART ports      */
    event(uart_intr, 0, UART_FLUSH_TIME);
}


static void
uart_irq_start()
{
#ifdef FAST_UART
    event(uart_intr, 0, UART_FLUSH_TIME);
#else
#ifndef _WIN32
    event(uart_rx, 0, UART_RX_TIME);
#endif
#endif
}

/* Watch-dog */

static void
wdog_intr(arg)
    caddr_t         arg;
{
    if (wdog_status == disabled) {
	wdog_status = stopped;
    } else {

	if (wdog_counter) {
	    wdog_counter--;
	    event(wdog_intr, 0, wdog_scaler + 1);
	} else {
	    if (wdog_rston) {
		printf("Watchdog reset!\n");
		sys_reset();
		mec_ersr = 0xC000;
	    } else {
		mec_irq(15);
		wdog_rston = 1;
		wdog_counter = wdog_rst_delay;
		event(wdog_intr, 0, wdog_scaler + 1);
	    }
	}
    }
}

static void
wdog_start()
{
    event(wdog_intr, 0, wdog_scaler + 1);
    if (sis_verbose)
	printf("Watchdog started, scaler = %d, counter = %d\n",
	       wdog_scaler, wdog_counter);
}


/* MEC timers */


static void
rtc_intr(arg)
    caddr_t         arg;
{
    if (rtc_counter == 0) {

	mec_irq(13);
	if (rtc_cr)
	    rtc_counter = rtc_reload;
	else
	    rtc_se = 0;
    } else
	rtc_counter -= 1;
    if (rtc_se) {
	event(rtc_intr, 0, rtc_scaler + 1);
	rtc_scaler_start = now();
	rtc_enabled = 1;
    } else {
	if (sis_verbose)
	    printf("RTC stopped\n\r");
	rtc_enabled = 0;
    }
}

static void
rtc_start()
{
    if (sis_verbose)
	printf("RTC started (period %d)\n\r", rtc_scaler + 1);
    event(rtc_intr, 0, rtc_scaler + 1);
    rtc_scaler_start = now();
    rtc_enabled = 1;
}

static uint32
rtc_counter_read()
{
    return (rtc_counter);
}

static void
rtc_scaler_set(val)
    uint32          val;
{
    rtc_scaler = val & 0x0ff;	/* eight-bit scaler only */
}

static void
rtc_reload_set(val)
    uint32          val;
{
    rtc_reload = val;
}

static void
gpt_intr(arg)
    caddr_t         arg;
{
    if (gpt_counter == 0) {
	mec_irq(12);
	if (gpt_cr)
	    gpt_counter = gpt_reload;
	else
	    gpt_se = 0;
    } else
	gpt_counter -= 1;
    if (gpt_se) {
	event(gpt_intr, 0, gpt_scaler + 1);
	gpt_scaler_start = now();
	gpt_enabled = 1;
    } else {
	if (sis_verbose)
	    printf("GPT stopped\n\r");
	gpt_enabled = 0;
    }
}

static void
gpt_start()
{
    if (sis_verbose)
	printf("GPT started (period %d)\n\r", gpt_scaler + 1);
    event(gpt_intr, 0, gpt_scaler + 1);
    gpt_scaler_start = now();
    gpt_enabled = 1;
}

static uint32
gpt_counter_read()
{
    return (gpt_counter);
}

static void
gpt_scaler_set(val)
    uint32          val;
{
    gpt_scaler = val & 0x0ffff;	/* 16-bit scaler */
}

static void
gpt_reload_set(val)
    uint32          val;
{
    gpt_reload = val;
}

static void
timer_ctrl(val)
    uint32          val;
{

    rtc_cr = ((val & TCR_TCRCR) != 0);
    if (val & TCR_TCRCL) {
	rtc_counter = rtc_reload;
    }
    if (val & TCR_TCRSL) {
    }
    rtc_se = ((val & TCR_TCRSE) != 0);
    if (rtc_se && (rtc_enabled == 0))
	rtc_start();

    gpt_cr = (val & TCR_GACR);
    if (val & TCR_GACL) {
	gpt_counter = gpt_reload;
    }
    if (val & TCR_GACL) {
    }
    gpt_se = (val & TCR_GASE) >> 2;
    if (gpt_se && (gpt_enabled == 0))
	gpt_start();
}


/* Retrieve data from target memory.  MEM points to location from which
   to read the data; DATA points to words where retrieved data will be
   stored in host byte order.  SZ contains log(2) of the number of bytes
   to retrieve, and can be 0 (1 byte), 1 (one half-word), 2 (one word),
   or 3 (two words). */

static void
fetch_bytes (asi, mem, data, sz)
    int		    asi;
    unsigned char  *mem;
    uint32	   *data;
    int		    sz;
{
    if (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN
	|| asi == 8 || asi == 9) {
	switch (sz) {
	case 3:
	    data[1] =  (((uint32) mem[7]) & 0xff) |
		      ((((uint32) mem[6]) & 0xff) <<  8) |
		      ((((uint32) mem[5]) & 0xff) << 16) |
		      ((((uint32) mem[4]) & 0xff) << 24);
	    /* Fall through to 2 */
	case 2:
	    data[0] =  (((uint32) mem[3]) & 0xff) |
		      ((((uint32) mem[2]) & 0xff) <<  8) |
		      ((((uint32) mem[1]) & 0xff) << 16) |
		      ((((uint32) mem[0]) & 0xff) << 24);
	    break;
	case 1:
	    data[0] =  (((uint32) mem[1]) & 0xff) |
		      ((((uint32) mem[0]) & 0xff) << 8);
	    break;
	case 0:
	    data[0] = mem[0] & 0xff;
	    break;
	    
	}
    } else {
	switch (sz) {
	case 3:
	    data[1] = ((((uint32) mem[7]) & 0xff) << 24) |
		      ((((uint32) mem[6]) & 0xff) << 16) |
		      ((((uint32) mem[5]) & 0xff) <<  8) |
		       (((uint32) mem[4]) & 0xff);
	    /* Fall through to 4 */
	case 2:
	    data[0] = ((((uint32) mem[3]) & 0xff) << 24) |
		      ((((uint32) mem[2]) & 0xff) << 16) |
		      ((((uint32) mem[1]) & 0xff) <<  8) |
		       (((uint32) mem[0]) & 0xff);
	    break;
	case 1:
	    data[0] = ((((uint32) mem[1]) & 0xff) <<  8) |
		       (((uint32) mem[0]) & 0xff);
	    break;
	case 0:
	    data[0] = mem[0] & 0xff;
	    break;
	}
    }
}


/* Store data in target byte order.  MEM points to location to store data;
   DATA points to words in host byte order to be stored.  SZ contains log(2)
   of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
   2 (one word), or 3 (two words). */

static void
store_bytes (mem, data, sz)
    unsigned char  *mem;
    uint32	   *data;
    int		    sz;
{
    if (CURRENT_TARGET_BYTE_ORDER == LITTLE_ENDIAN) {
	switch (sz) {
	case 3:
	    mem[7] = (data[1] >> 24) & 0xff;
	    mem[6] = (data[1] >> 16) & 0xff;
	    mem[5] = (data[1] >>  8) & 0xff;
	    mem[4] = data[1] & 0xff;
	    /* Fall through to 2 */
	case 2:
	    mem[3] = (data[0] >> 24) & 0xff;
	    mem[2] = (data[0] >> 16) & 0xff;
	    /* Fall through to 1 */
	case 1:
	    mem[1] = (data[0] >>  8) & 0xff;
	    /* Fall through to 0 */
	case 0:
	    mem[0] = data[0] & 0xff;
	    break;
	}
    } else {
	switch (sz) {
	case 3:
	    mem[7] = data[1] & 0xff;
	    mem[6] = (data[1] >>  8) & 0xff;
	    mem[5] = (data[1] >> 16) & 0xff;
	    mem[4] = (data[1] >> 24) & 0xff;
	    /* Fall through to 2 */
	case 2:
	    mem[3] = data[0] & 0xff;
	    mem[2] = (data[0] >>  8) & 0xff;
	    mem[1] = (data[0] >> 16) & 0xff;
	    mem[0] = (data[0] >> 24) & 0xff;
	    break;
	case 1:
	    mem[1] = data[0] & 0xff;
	    mem[0] = (data[0] >> 8) & 0xff;
	    break;
	case 0:
	    mem[0] = data[0] & 0xff;
	    break;
	    
	}
    }
}


/* Memory emulation */

int
memory_read(asi, addr, data, sz, ws)
    int32           asi;
    uint32          addr;
    uint32         *data;
    int32           sz;
    int32          *ws;
{
    int32           mexc;

#ifdef ERRINJ
    if (errmec) {
	if (sis_verbose)
	    printf("Inserted MEC error %d\n",errmec);
	set_sfsr(errmec, addr, asi, 1);
	if (errmec == 5) mecparerror();
	if (errmec == 6) iucomperr();
	errmec = 0;
	return(1);
    }
#endif;

    if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
	fetch_bytes (asi, &ramb[addr & mem_rammask], data, sz);
	*ws = mem_ramr_ws;
	return (0);
    } else if ((addr >= MEC_START) && (addr < MEC_END)) {
	mexc = mec_read(addr, asi, data);
	if (mexc) {
	    set_sfsr(MEC_ACC, addr, asi, 1);
	    *ws = MEM_EX_WS;
	} else {
	    *ws = 0;
	}
	return (mexc);

#ifdef ERA

    } else if (era) {
    	if ((addr < 0x100000) || 
	    ((addr>= 0x80000000) && (addr < 0x80100000))) {
	    fetch_bytes (asi, &romb[addr & ROM_MASK], data, sz);
	    *ws = 4;
	    return (0);
	} else if ((addr >= 0x10000000) && 
		   (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
		   (mec_iocr & 0x10))  {
	    *data = erareg;
	    return (0);
	}
	
    } else  if (addr < mem_romsz) {
	    fetch_bytes (asi, &romb[addr], data, sz);
	    *ws = mem_romr_ws;
	    return (0);

#else
    } else if (addr < mem_romsz) {
	fetch_bytes (asi, &romb[addr], data, sz);
	*ws = mem_romr_ws;
	return (0);
#endif

    }

    printf("Memory exception at %x (illegal address)\n", addr);
    set_sfsr(UIMP_ACC, addr, asi, 1);
    *ws = MEM_EX_WS;
    return (1);
}

int
memory_write(asi, addr, data, sz, ws)
    int32           asi;
    uint32          addr;
    uint32         *data;
    int32           sz;
    int32          *ws;
{
    uint32          byte_addr;
    uint32          byte_mask;
    uint32          waddr;
    uint32         *ram;
    int32           mexc;
    int             i;
    int             wphit[2];

#ifdef ERRINJ
    if (errmec) {
	if (sis_verbose)
	    printf("Inserted MEC error %d\n",errmec);
	set_sfsr(errmec, addr, asi, 0);
	if (errmec == 5) mecparerror();
	if (errmec == 6) iucomperr();
	errmec = 0;
	return(1);
    }
#endif;

    if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
	if (mem_accprot) {

	    waddr = (addr & 0x7fffff) >> 2;
	    for (i = 0; i < 2; i++)
		wphit[i] =
		    (((asi == 0xa) && (mec_wpr[i] & 1)) ||
		     ((asi == 0xb) && (mec_wpr[i] & 2))) &&
		    ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));

	    if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
		((!mem_blockprot) &&
		 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
		 )) {
		if (sis_verbose)
		    printf("Memory access protection error at 0x%08x\n", addr);
		set_sfsr(PROT_EXC, addr, asi, 0);
		*ws = MEM_EX_WS;
		return (1);
	    }
	}

	store_bytes (&ramb[addr & mem_rammask], data, sz);

	switch (sz) {
	case 0:
	case 1:
	    *ws = mem_ramw_ws + 3;
	    break;
	case 2:
	    *ws = mem_ramw_ws;
	    break;
	case 3:
	    *ws = 2 * mem_ramw_ws + STD_WS;
	    break;
	}
	return (0);
    } else if ((addr >= MEC_START) && (addr < MEC_END)) {
	if ((sz != 2) || (asi != 0xb)) {
	    set_sfsr(MEC_ACC, addr, asi, 0);
	    *ws = MEM_EX_WS;
	    return (1);
	}
	mexc = mec_write(addr, *data);
	if (mexc) {
	    set_sfsr(MEC_ACC, addr, asi, 0);
	    *ws = MEM_EX_WS;
	} else {
	    *ws = 0;
	}
	return (mexc);

#ifdef ERA

    } else if (era) {
    	if ((erareg & 2) && 
	((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
	    addr &= ROM_MASK;
	    *ws = sz == 3 ? 8 : 4;
	    store_bytes (&romb[addr], data, sz);
            return (0);
	} else if ((addr >= 0x10000000) && 
		   (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
		   (mec_iocr & 0x10))  {
	    erareg = *data & 0x0e;
	    return (0);
	}

    } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
               (((mec_memcfg & 0x20000) && (sz > 1)) || 
		(!(mec_memcfg & 0x20000) && (sz == 0)))) {

	*ws = mem_romw_ws + 1;
	if (sz == 3)
	    *ws += mem_romw_ws + STD_WS;
	store_bytes (&romb[addr], data, sz);
        return (0);

#else
    } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
               (((mec_memcfg & 0x20000) && (sz > 1)) || 
		(!(mec_memcfg & 0x20000) && (sz == 0)))) {

	*ws = mem_romw_ws + 1;
	if (sz == 3)
            *ws += mem_romw_ws + STD_WS;
	store_bytes (&romb[addr], data, sz);
        return (0);

#endif

    }
	
    *ws = MEM_EX_WS;
    set_sfsr(UIMP_ACC, addr, asi, 0);
    return (1);
}

static unsigned char  *
get_mem_ptr(addr, size)
    uint32          addr;
    uint32          size;
{
    if ((addr + size) < ROM_SZ) {
	return (&romb[addr]);
    } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
	return (&ramb[addr & mem_rammask]);
    }

#ifdef ERA
      else if ((era) && ((addr <0x100000) || 
	((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
	return (&romb[addr & ROM_MASK]);
    }
#endif

    return ((char *) -1);
}

int
sis_memory_write(addr, data, length)
    uint32          addr;
    char           *data;
    uint32          length;
{
    char           *mem;

    if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
	return (0);

    memcpy(mem, data, length);
    return (length);
}

int
sis_memory_read(addr, data, length)
    uint32          addr;
    char           *data;
    uint32          length;
{
    char           *mem;

    if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
	return (0);

    memcpy(data, mem, length);
    return (length);
}