📄 task2.lss
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// compare mode is used. Add code that sets the CMP register to the half of
// the ADCA resolution
ADCA.CMP = (0x800 / 2);
30e: 80 e0 ldi r24, 0x00 ; 0
310: 94 e0 ldi r25, 0x04 ; 4
312: f8 01 movw r30, r16
314: 80 8f std Z+24, r24 ; 0x18
316: 91 8f std Z+25, r25 ; 0x19
// Wait until common mode voltage is stable. Default clk is 2MHz and
// therefore below the maximum frequency to use this function.
ADC_Wait_8MHz(&ADCA);
318: 80 e0 ldi r24, 0x00 ; 0
31a: 92 e0 ldi r25, 0x02 ; 2
31c: 0e 94 c5 01 call 0x38a ; 0x38a <ADC_Wait_8MHz>
// Setup Interrupt Mode Above Compare Value (ADCA.CMP)
ADC_Ch_Interrupts_Config( &ADCA.CH0,
320: f7 01 movw r30, r14
322: 82 81 ldd r24, Z+2 ; 0x02
324: 80 7f andi r24, 0xF0 ; 240
326: 8e 60 ori r24, 0x0E ; 14
328: 82 83 std Z+2, r24 ; 0x02
ADC_CH_INTMODE_ABOVE_gc,
ADC_CH_INTLVL_MED_gc);
// Enable the Medium Level interrupts needed in the PMIC
// ADD CODE HERE
PMIC.CTRL |= PMIC_MEDLVLEN_bm;
32a: e0 ea ldi r30, 0xA0 ; 160
32c: f0 e0 ldi r31, 0x00 ; 0
32e: 82 81 ldd r24, Z+2 ; 0x02
330: 82 60 ori r24, 0x02 ; 2
332: 82 83 std Z+2, r24 ; 0x02
// Enable free running mode
ADC_FreeRunning_Enable(&ADCA);
334: f8 01 movw r30, r16
336: 81 81 ldd r24, Z+1 ; 0x01
338: 88 60 ori r24, 0x08 ; 8
33a: 81 83 std Z+1, r24 ; 0x01
// Enable ADC A
ADC_Enable(&ADCA);
33c: 80 81 ld r24, Z
33e: 81 60 ori r24, 0x01 ; 1
340: 80 83 st Z, r24
// Enable Global interrupts
sei();
342: 78 94 sei
while(1)
{
// Invert the output since a pin high is LED off
LEDPORT.OUT = ~ADC_result;
344: e0 e6 ldi r30, 0x60 ; 96
346: f6 e0 ldi r31, 0x06 ; 6
348: 80 91 00 20 lds r24, 0x2000
34c: 90 91 01 20 lds r25, 0x2001
350: 80 95 com r24
352: 84 83 std Z+4, r24 ; 0x04
354: f9 cf rjmp .-14 ; 0x348 <main+0x98>
00000356 <ADC_ResultCh_GetWord>:
* \param adc_ch Pointer to ADC channel register section.
* \param offset Offset value that is compansated for.
* \return Conversion result.
*/
uint16_t ADC_ResultCh_GetWord(ADC_CH_t * adc_ch, uint8_t offset)
{
356: fc 01 movw r30, r24
uint16_t answer;
uint16_t signedOffset = (uint16_t) offset;
358: 26 2f mov r18, r22
35a: 30 e0 ldi r19, 0x00 ; 0
/* Append 16-bit signed value if offset (signed) is negative. */
if (offset >= 128){
35c: 66 23 and r22, r22
35e: 0c f4 brge .+2 ; 0x362 <ADC_ResultCh_GetWord+0xc>
signedOffset |= 0xFF00;
360: 3f 6f ori r19, 0xFF ; 255
}
/* Clear interrupt flag.*/
adc_ch->INTFLAGS = ADC_CH_CHIF_bm;
362: 81 e0 ldi r24, 0x01 ; 1
364: 83 83 std Z+3, r24 ; 0x03
/* Return result register contents*/
answer = adc_ch->RES + signedOffset;
366: 84 81 ldd r24, Z+4 ; 0x04
368: 95 81 ldd r25, Z+5 ; 0x05
36a: 28 0f add r18, r24
36c: 39 1f adc r19, r25
return answer;
}
36e: 82 2f mov r24, r18
370: 93 2f mov r25, r19
372: 08 95 ret
00000374 <ADC_ResultCh_GetLowByte>:
* \param offset Compansation offset value.
*
* \return Low byte of conversion result.
*/
uint8_t ADC_ResultCh_GetLowByte(ADC_CH_t * adc_ch, uint8_t offset)
{
374: fc 01 movw r30, r24
uint8_t answer;
/* Clear interrupt flag.*/
adc_ch->INTFLAGS = ADC_CH_CHIF_bm;
376: 81 e0 ldi r24, 0x01 ; 1
378: 83 83 std Z+3, r24 ; 0x03
/* Return result register contents*/
answer = adc_ch->RESL - offset;
37a: 84 81 ldd r24, Z+4 ; 0x04
return answer;
}
37c: 86 1b sub r24, r22
37e: 08 95 ret
00000380 <ADC_ResultCh_GetHighByte>:
* \param adc_ch Pointer to ADC channel register section.
*
* \return High byte of conversion result.
*/
uint8_t ADC_ResultCh_GetHighByte(ADC_CH_t * adc_ch)
{
380: fc 01 movw r30, r24
/* Clear interrupt flag.*/
adc_ch->INTFLAGS = ADC_CH_CHIF_bm;
382: 81 e0 ldi r24, 0x01 ; 1
384: 83 83 std Z+3, r24 ; 0x03
/* Return low byte result register contents.*/
return adc_ch->RESH;
386: 85 81 ldd r24, Z+5 ; 0x05
}
388: 08 95 ret
0000038a <ADC_Wait_8MHz>:
* than 8 MHz use the ADC_wait_32MHz function.
*
* \param adc Pointer to ADC module register section.
*/
void ADC_Wait_8MHz(ADC_t * adc)
{
38a: fc 01 movw r30, r24
/* Store old prescaler value. */
uint8_t prescaler_val = adc->PRESCALER;
38c: 84 81 ldd r24, Z+4 ; 0x04
/* Set prescaler value to minimum value. */
adc->PRESCALER = ADC_PRESCALER_DIV4_gc;
38e: 14 82 std Z+4, r1 ; 0x04
can be achieved.
*/
void
_delay_loop_1(uint8_t __count)
{
__asm__ volatile (
390: 9a e2 ldi r25, 0x2A ; 42
392: 9a 95 dec r25
394: f1 f7 brne .-4 ; 0x392 <ADC_Wait_8MHz+0x8>
/* Wait 4*COMMON_MODE_CYCLES for common mode to settle. */
delay_us(4*COMMON_MODE_CYCLES);
/* Set prescaler to old value*/
adc->PRESCALER = prescaler_val;
396: 84 83 std Z+4, r24 ; 0x04
}
398: 08 95 ret
0000039a <ADC_Wait_32MHz>:
* device goes into sleep (not Idle sleep mode).
*
* \param adc Pointer to ADC module register section.
*/
void ADC_Wait_32MHz(ADC_t * adc)
{
39a: fc 01 movw r30, r24
/* Store old prescaler value. */
uint8_t prescaler_val = adc->PRESCALER;
39c: 94 81 ldd r25, Z+4 ; 0x04
/* Set prescaler value to minimum value. */
adc->PRESCALER = ADC_PRESCALER_DIV8_gc;
39e: 81 e0 ldi r24, 0x01 ; 1
3a0: 84 83 std Z+4, r24 ; 0x04
3a2: 85 e5 ldi r24, 0x55 ; 85
3a4: 8a 95 dec r24
3a6: f1 f7 brne .-4 ; 0x3a4 <ADC_Wait_32MHz+0xa>
/* wait 8*COMMON_MODE_CYCLES for common mode to settle*/
delay_us(8*COMMON_MODE_CYCLES);
/* Set prescaler to old value*/
adc->PRESCALER = prescaler_val;
3a8: 94 83 std Z+4, r25 ; 0x04
}
3aa: 08 95 ret
000003ac <ADC_Offset_Get>:
* \param adc Pointer to the ADC to calculate offset from.
*
* \return Offset on the selected ADC
*/
uint8_t ADC_Offset_Get(ADC_t * adc)
{
3ac: cf 93 push r28
3ae: df 93 push r29
3b0: ec 01 movw r28, r24
uint8_t offset;
/* Set up ADC to get offset. */
ADC_ConvMode_and_Resolution_Config(adc, true, ADC_RESOLUTION_12BIT_gc);
3b2: 89 81 ldd r24, Y+1 ; 0x01
3b4: 89 7e andi r24, 0xE9 ; 233
3b6: 80 61 ori r24, 0x10 ; 16
3b8: 89 83 std Y+1, r24 ; 0x01
ADC_Prescaler_Config(adc , ADC_PRESCALER_DIV8_gc);
3ba: 8c 81 ldd r24, Y+4 ; 0x04
3bc: 88 7f andi r24, 0xF8 ; 248
3be: 81 60 ori r24, 0x01 ; 1
3c0: 8c 83 std Y+4, r24 ; 0x04
ADC_Reference_Config(adc , ADC_REFSEL_VCC_gc);
3c2: 8a 81 ldd r24, Y+2 ; 0x02
3c4: 8f 7c andi r24, 0xCF ; 207
3c6: 80 61 ori r24, 0x10 ; 16
3c8: 8a 83 std Y+2, r24 ; 0x02
ADC_Ch_InputMode_and_Gain_Config(&(adc->CH0),
3ca: 88 a1 ldd r24, Y+32 ; 0x20
3cc: 80 7e andi r24, 0xE0 ; 224
3ce: 82 60 ori r24, 0x02 ; 2
3d0: 88 a3 std Y+32, r24 ; 0x20
ADC_CH_INPUTMODE_DIFF_gc,
ADC_CH_GAIN_1X_gc);
ADC_Ch_InputMux_Config(&(adc->CH0), ADC_CH_MUXPOS_PIN0_gc, ADC_CH_MUXNEG_PIN0_gc);
3d2: 19 a2 std Y+33, r1 ; 0x21
/* Enable ADC. */
ADC_Enable(adc);
3d4: 88 81 ld r24, Y
3d6: 81 60 ori r24, 0x01 ; 1
3d8: 88 83 st Y, r24
/* Wait until ADC is ready. */
ADC_Wait_32MHz(adc);
3da: ce 01 movw r24, r28
3dc: 0e 94 cd 01 call 0x39a ; 0x39a <ADC_Wait_32MHz>
/* Do one conversion to find offset. */
ADC_Ch_Conversion_Start(&(adc->CH0));
3e0: 88 a1 ldd r24, Y+32 ; 0x20
3e2: 80 68 ori r24, 0x80 ; 128
3e4: 88 a3 std Y+32, r24 ; 0x20
do{
}while(!ADC_Ch_Conversion_Complete(&(adc->CH0)));
3e6: 8b a1 ldd r24, Y+35 ; 0x23
3e8: 80 ff sbrs r24, 0
3ea: fd cf rjmp .-6 ; 0x3e6 <ADC_Offset_Get+0x3a>
offset = ADC_ResultCh_GetLowByte(&(adc->CH0), 0x00);
3ec: 60 e0 ldi r22, 0x00 ; 0
3ee: ce 01 movw r24, r28
3f0: 80 96 adiw r24, 0x20 ; 32
3f2: 0e 94 ba 01 call 0x374 ; 0x374 <ADC_ResultCh_GetLowByte>
/* Disable ADC. */
ADC_Disable(adc);
3f6: 98 81 ld r25, Y
3f8: 9e 7f andi r25, 0xFE ; 254
3fa: 98 83 st Y, r25
return offset;
}
3fc: df 91 pop r29
3fe: cf 91 pop r28
400: 08 95 ret
00000402 <SP_ReadCalibrationByte>:
* \param index The index to the calibration byte.
*
* \return Calibration byte.
*/
uint8_t SP_ReadCalibrationByte( uint8_t index ){return 0;}
402: 80 e0 ldi r24, 0x00 ; 0
404: 08 95 ret
00000406 <ADC_CalibrationValues_Set>:
* register. The calibration data reduces the gain error in the adc.
*
* \param adc Pointer to ADC module register section.
*/
void ADC_CalibrationValues_Set(ADC_t * adc)
{
406: cf 93 push r28
408: df 93 push r29
40a: ec 01 movw r28, r24
if(&ADCA == adc){
40c: 82 e0 ldi r24, 0x02 ; 2
40e: c0 30 cpi r28, 0x00 ; 0
410: d8 07 cpc r29, r24
412: 39 f4 brne .+14 ; 0x422 <ADC_CalibrationValues_Set+0x1c>
/* Get ADCCAL0 from byte address 0x20 (Word address 0x10. */
adc->CALIB = SP_ReadCalibrationByte(0x20);
414: 80 e2 ldi r24, 0x20 ; 32
416: 0e 94 01 02 call 0x402 ; 0x402 <SP_ReadCalibrationByte>
41a: e0 e0 ldi r30, 0x00 ; 0
41c: f2 e0 ldi r31, 0x02 ; 2
41e: 84 87 std Z+12, r24 ; 0x0c
420: 04 c0 rjmp .+8 ; 0x42a <ADC_CalibrationValues_Set+0x24>
}else {
/* Get ADCCAL0 from byte address 0x24 (Word address 0x12. */
adc->CALIB = SP_ReadCalibrationByte(0x24);
422: 84 e2 ldi r24, 0x24 ; 36
424: 0e 94 01 02 call 0x402 ; 0x402 <SP_ReadCalibrationByte>
428: 8c 87 std Y+12, r24 ; 0x0c
}
}
42a: df 91 pop r29
42c: cf 91 pop r28
42e: 08 95 ret
00000430 <_exit>:
430: f8 94 cli
00000432 <__stop_program>:
432: ff cf rjmp .-2 ; 0x432 <__stop_program>
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