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📄 gmsk.mdl

📁 gsm通信中
💻 MDL
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	      ReqsInCode	      off
	    }
	    Simulink.GRTTargetCC {
	      $BackupClass	      "Simulink.TargetCC"
	      $ObjectID		      10
	      Array {
		Type			"Cell"
		Dimension		16
		Cell			"IncludeMdlTerminateFcn"
		Cell			"CombineOutputUpdateFcns"
		Cell			"SuppressErrorStatus"
		Cell			"ERTCustomFileBanners"
		Cell			"GenerateSampleERTMain"
		Cell			"GenerateTestInterfaces"
		Cell			"ModelStepFunctionPrototypeControlCompliant"
		Cell			"CPPClassGenCompliant"
		Cell			"MultiInstanceERTCode"
		Cell			"PurelyIntegerCode"
		Cell			"SupportNonFinite"
		Cell			"SupportComplex"
		Cell			"SupportAbsoluteTime"
		Cell			"SupportContinuousTime"
		Cell			"SupportNonInlinedSFcns"
		Cell			"PortableWordSizes"
		PropName		"DisabledProps"
	      }
	      Version		      "1.4.0"
	      TargetFcnLib	      "ansi_tfl_table_tmw.mat"
	      TargetLibSuffix	      ""
	      TargetPreCompLibLocation ""
	      TargetFunctionLibrary   "ANSI_C"
	      UtilityFuncGeneration   "Auto"
	      GenerateFullHeader      on
	      GenerateSampleERTMain   off
	      GenerateTestInterfaces  off
	      IsPILTarget	      off
	      ModelReferenceCompliant on
	      CompOptLevelCompliant   on
	      IncludeMdlTerminateFcn  on
	      CombineOutputUpdateFcns off
	      SuppressErrorStatus     off
	      ERTFirstTimeCompliant   off
	      IncludeFileDelimiter    "Auto"
	      ERTCustomFileBanners    off
	      SupportAbsoluteTime     on
	      LogVarNameModifier      "rt_"
	      MatFileLogging	      on
	      MultiInstanceERTCode    off
	      SupportNonFinite	      on
	      SupportComplex	      on
	      PurelyIntegerCode	      off
	      SupportContinuousTime   on
	      SupportNonInlinedSFcns  on
	      EnableShiftOperators    on
	      ParenthesesLevel	      "Nominal"
	      PortableWordSizes	      off
	      ModelStepFunctionPrototypeControlCompliant off
	      AutosarCompliant	      off
	      ExtMode		      off
	      ExtModeStaticAlloc      off
	      ExtModeTesting	      off
	      ExtModeStaticAllocSize  1000000
	      ExtModeTransport	      0
	      ExtModeMexFile	      "ext_comm"
	      ExtModeIntrfLevel	      "Level1"
	      RTWCAPISignals	      off
	      RTWCAPIParams	      off
	      RTWCAPIStates	      off
	      GenerateASAP2	      off
	    }
	    PropName		    "Components"
	  }
	}
	hdlcoderui.hdlcc {
	  $ObjectID		  11
	  Description		  "HDL Coder custom configuration component"
	  Version		  "1.4.0"
	  Name			  "HDL Coder"
	  Array {
	    Type		    "Cell"
	    Dimension		    1
	    Cell		    ""
	    PropName		    "HDLConfigFile"
	  }
	  HDLCActiveTab		  "0"
	}
	PropName		"Components"
      }
      Name		      "Configuration"
      CurrentDlgPage	      "Solver"
    }
    PropName		    "ConfigurationSets"
  }
  Simulink.ConfigSet {
    $PropName		    "ActiveConfigurationSet"
    $ObjectID		    1
  }
  BlockDefaults {
    Orientation		    "right"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    NamePlacement	    "normal"
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    ShowName		    on
  }
  BlockParameterDefaults {
    Block {
      BlockType		      Ground
    }
    Block {
      BlockType		      Inport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      OutMin		      "[]"
      OutMax		      "[]"
      DataType		      "auto"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: auto"
      SignalType	      "auto"
      SamplingMode	      "auto"
      LatchByDelayingOutsideSignal off
      LatchByCopyingInsideSignal off
      Interpolate	      on
    }
    Block {
      BlockType		      Outport
      Port		      "1"
      UseBusObject	      off
      BusObject		      "BusObject"
      BusOutputAsStruct	      off
      PortDimensions	      "-1"
      SampleTime	      "-1"
      OutMin		      "[]"
      OutMax		      "[]"
      DataType		      "auto"
      OutDataType	      "fixdt(1,16,0)"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: auto"
      SignalType	      "auto"
      SamplingMode	      "auto"
      OutputWhenDisabled      "held"
      InitialOutput	      "[]"
    }
    Block {
      BlockType		      "S-Function"
      FunctionName	      "system"
      SFunctionModules	      "''"
      PortCounts	      "[]"
      SFunctionDeploymentMode off
    }
    Block {
      BlockType		      SubSystem
      ShowPortLabels	      "FromPortIcon"
      Permissions	      "ReadWrite"
      PermitHierarchicalResolution "All"
      TreatAsAtomicUnit	      off
      CheckFcnCallInpInsideContextMsg off
      SystemSampleTime	      "-1"
      RTWFcnNameOpts	      "Auto"
      RTWFileNameOpts	      "Auto"
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      SimViewingDevice	      off
      DataTypeOverride	      "UseLocalSettings"
      MinMaxOverflowLogging   "UseLocalSettings"
    }
    Block {
      BlockType		      FrameConversion
      InheritSamplingMode     off
      OutFrame		      "Frame-based"
    }
    Block {
      BlockType		      Reshape
      OutputDimensionality    "1-D array"
      OutputDimensions	      "[1,1]"
    }
    Block {
      BlockType		      Constant
      Value		      "1"
      VectorParams1D	      on
      SamplingMode	      "Sample based"
      OutMin		      "[]"
      OutMax		      "[]"
      OutDataTypeMode	      "Inherit from 'Constant value'"
      OutDataType	      "fixdt(1,16,0)"
      ConRadixGroup	      "Use specified scaling"
      OutScaling	      "[]"
      OutDataTypeStr	      "Inherit: Inherit from 'Constant value'"
      SampleTime	      "inf"
      FramePeriod	      "inf"
    }
    Block {
      BlockType		      RelationalOperator
      Operator		      ">="
      InputSameDT	      on
      LogicOutDataTypeMode    "Logical (see Configuration Parameters: Optimization)"
      LogicDataType	      "uint(8)"
      OutDataTypeStr	      "Inherit: Logical (see Configuration Parameters: Optimization)"
      ZeroCross		      on
      SampleTime	      "-1"
    }
  }
  AnnotationDefaults {
    HorizontalAlignment	    "center"
    VerticalAlignment	    "middle"
    ForegroundColor	    "black"
    BackgroundColor	    "white"
    DropShadow		    off
    FontName		    "Helvetica"
    FontSize		    10
    FontWeight		    "normal"
    FontAngle		    "normal"
    UseDisplayTextAsClickCallback off
  }
  LineDefaults {
    FontName		    "Helvetica"
    FontSize		    9
    FontWeight		    "normal"
    FontAngle		    "normal"
  }
  System {
    Name		    "gmsk"
    Location		    [270, 380, 1028, 675]
    Open		    on
    ModelBrowserVisibility  off
    ModelBrowserWidth	    200
    ScreenColor		    "white"
    PaperOrientation	    "landscape"
    PaperPositionMode	    "auto"
    PaperType		    "A4"
    PaperUnits		    "centimeters"
    TiledPaperMargins	    [0.500000, 0.500000, 0.500000, 0.500000]
    TiledPageScale	    1
    ShowPageBoundaries	    off
    ZoomFactor		    "100"
    ReportName		    "simulink-default.rpt"
    Block {
      BlockType		      Reference
      Name		      "AWGN\nChannel"
      Ports		      [1, 1]
      Position		      [265, 76, 360, 134]
      SourceBlock	      "commchan3/AWGN\nChannel"
      SourceType	      "AWGN Channel"
      ShowPortLabels	      "FromPortIcon"
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      seed		      "67"
      noiseMode		      "Signal to noise ratio  (SNR)"
      EbNodB		      "10"
      EsNodB		      "10"
      SNRdB		      "xSNR"
      bitsPerSym	      "1"
      Ps		      "1"
      Tsym		      "1"
      variance		      "1"
    }
    Block {
      BlockType		      Reference
      Name		      "Bernoulli Binary\nGenerator"
      Ports		      [0, 1]
      Position		      [15, 83, 95, 127]
      DialogController	      "commDDGCreate"
      DialogControllerArgs    "DataTag0"
      FontName		      "Arial"
      SourceBlock	      "commrandsrc2/Bernoulli Binary\nGenerator"
      SourceType	      "Bernoulli Binary Generator"
      ShowPortLabels	      "FromPortIcon"
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      P			      "0.5"
      seed		      "xInitialSeed"
      Ts		      "xSampleTime"
      frameBased	      off
      sampPerFrame	      "1"
      orient		      off
      outDataType	      "double"
    }
    Block {
      BlockType		      Reference
      Name		      "Error Rate\nCalculation"
      Ports		      [2]
      Position		      [560, 67, 635, 118]
      SourceBlock	      "commsink2/Error Rate\nCalculation"
      SourceType	      "Error Rate Calculation"
      N			      "xTracebackLength+1"
      st_delay		      "0"
      cp_mode		      "Entire frame"
      subframe		      "[]"
      PMode		      "Workspace"
      WsName		      "xErrorRate"
      RsMode2		      off
      stop		      off
      numErr		      "100"
      maxBits		      "1e6"
    }
    Block {
      BlockType		      Reference
      Name		      "GMSK\nDemodulator\nBaseband"
      Ports		      [1, 1]
      Position		      [395, 79, 470, 131]
      SourceBlock	      "commdigbbndcpm2/GMSK\nDemodulator\nBaseband"
      SourceType	      "GMSK Demodulator Baseband"
      ShowPortLabels	      "FromPortIcon"
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      OutputType	      "Bit"
      BT		      ".3"
      pulseLength	      "4"
      preHistory	      "1"
      phaseOffset	      "0"
      samplesPerSymbol	      "1"
      traceBack		      "xTracebackLength"
      outDType		      "double"
    }
    Block {
      BlockType		      Reference
      Name		      "GMSK\nModulator\nBaseband"
      Ports		      [1, 1]
      Position		      [140, 79, 215, 131]
      SourceBlock	      "commdigbbndcpm2/GMSK\nModulator\nBaseband"
      SourceType	      "GMSK Modulator Baseband"
      ShowPortLabels	      "FromPortIcon"
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      inputType		      "Bit"
      BT		      "0.3"
      pulseLength	      "4"
      preHistory	      "1"
      phaseOffset	      "0"
      samplesPerSymbol	      "1"
      outDataType	      "double"
    }
    Line {
      SrcBlock		      "Bernoulli Binary\nGenerator"
      SrcPort		      1
      Points		      [20, 0]
      Branch {
	DstBlock		"GMSK\nModulator\nBaseband"
	DstPort			1
      }
      Branch {
	Points			[0, -75; 390, 0; 0, 50]
	DstBlock		"Error Rate\nCalculation"
	DstPort			1
      }
    }
    Line {
      SrcBlock		      "GMSK\nModulator\nBaseband"
      SrcPort		      1
      DstBlock		      "AWGN\nChannel"
      DstPort		      1
    }
    Line {
      SrcBlock		      "AWGN\nChannel"
      SrcPort		      1
      DstBlock		      "GMSK\nDemodulator\nBaseband"
      DstPort		      1
    }
    Line {
      SrcBlock		      "GMSK\nDemodulator\nBaseband"
      SrcPort		      1
      DstBlock		      "Error Rate\nCalculation"
      DstPort		      2
    }
  }
}
MatData {
  NumRecords		  1
  DataRecord {
    Tag			    DataTag0
    Data		    "  %)30     .    >     8    (     0         %    \"     $    !     0         .    2     8    (    !          %    \"     $    2     0         0    $@   $)E<FYO=6QL:4)I;F%R>4=E;@        "
  }
}

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