dvhdmirxr8j66030ft.c

the HDMI(High Definition Multimedia Interface) driver code

#include "itron.h"
#include "kernel.h"
#include "dvCom.h"
#include "dvAPI.h"
#include "dtvc4_io.h"
#include "dvHdmiRx.h"
#include "dvHdmiRxLocal.h"
#include "dvHdmiRxR8J66030FT.h"
#include <stdio.h>

// R8J66030FT儗僕僗僞忣曬峔憿懱
typedef struct _TdvHdmiRxR8J66030FTReg {
	UB	IntrMaskReg[3];			//!< 妱崬傒儗僕僗僞				0x29
	UB	UserPacketReg1;			//!< 儐乕僓乕娔帇儗僕僗僞1		0x2D
	UB	UserPacketReg2;			//!< 儐乕僓乕娔帇儗僕僗僞2		0x2E
	UB	StatusReg0;				//!< 僗僥乕僞僗儗僕僗僞0		0x3C
	UB	StatusReg1;				//!< 僗僥乕僞僗儗僕僗僞1		0x3D
	UB	GeneralControlReg0;		//!< GeneralControl儗僕僗僞0	0x40
	UB	GeneralControlReg1;		//!< GeneralControl儗僕僗僞1	0x41
	UB	GeneralControlReg2;		//!< GeneralControl儗僕僗僞2	0x42
	UB	GeneralControlReg3;		//!< GeneralControl儗僕僗僞3	0x43
	UB	GeneralControlReg4;		//!< GeneralControl儗僕僗僞4	0x44
	UB	GeneralControlReg5;		//!< GeneralControl儗僕僗僞5	0x45
	UB	GeneralControlReg6;		//!< GeneralControl儗僕僗僞6	0x46
	UB	GeneralControlReg8;		//!< GeneralControl儗僕僗僞8	0x48
	UB	GeneralControlReg9;		//!< GeneralControl儗僕僗僞9	0x49
	UB	TimingReg[13];			//!< 僞僀儈儞僌儗僕僗僞			0x3B
} TdvHdmiRxR8J66030FTReg;

// IIC捠怣昗弨懸偪帪娫
#define IIC_WAIT_TIME	10

//  R8J66030FT儗僕僗僞 儈儔乕忣曬
static TdvHdmiRxR8J66030FTReg gHdmiRxDrvR8J66030FTReg;

// 僷働僢僩堦帪奿擺僶僢僼傽
/* #ACP_PACKET CHG S 2007/12/18 Y.Takeuchi */
static UB	gPacketDataBuff[31];
/* #ACP_PACKET CHG E 2007/12/18 Y.Takeuchi */

// 妱崬傒専弌捠抦CB娭悢
static void (*gHdmiRxDrvIntrCbFunc)(void);

//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//%%%%%%%%%% f-1  捠抦娭悢孮           %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//*******************************************************************
//! @brief		HDMI Rx 妱崬傒僴儞僪儔乕
//! @retval		<BR>
//! @param		<BR>
//! @note		<BR>
//! @attention	<BR>
//! @author		Y.Takeuchi
//! @date		07/04/13
//*******************************************************************
void _dvHdmiRxR8J66030FTIntruptHandler(void)
{
#ifdef HDMI_DEBUG
	UB	reg[3] = {0, 0, 0};
	IW ret;

	reg[0] = INTRUPT_ENABLE_REG_ADDR;
	ret = _HdmiRxDrvRegRead(DV_HDMIRX_DEF_SLAVE_ADDR, sizeof(reg), reg);
	if (ret == HDMIDRV_OK) {
		printf(" b0:%x b1:%x b2:%x\n", reg[0], reg[1], reg);
	}
#endif
	if (gHdmiRxDrvIntrCbFunc != NULL) {
		// 壖憐僪儔僀僶偺妱崬傒CB娭悢幚峴
		gHdmiRxDrvIntrCbFunc();
	}
}

//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//%%%%%%%%%% f-2  弶婜壔娭悢孮           %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
//*******************************************************************
//! @brief		HDMI Rx Drv 弶婜壔張棟
//! @retval		張棟寢壥
//! @param		<BR>
//! @note		<BR>
//! @attention	<BR>
//! @author		Y.Takeuchi
//! @date		07/03/22
//*******************************************************************
IW	_dvHdmiRxR8J66030FTInit(void)
{
	IW ret = HDMIDRV_OK;

	// 僴乕僪僂僃傾儕僙僢僩
	ret = _dvHdmiRxR8J66030FTReset();
	if (ret != HDMIDRV_OK) {
		HdmiRxDrvErrCatch("_dvHdmiRxR8J66030FTInit failed %d\n", ret);
	}
	return ret;
}

//*******************************************************************
//! @brief		R8J66030FT偲偺娭楢晅偗
//! @retval		張棟寢壥
//! @param		<BR>
//! @note		<BR>
//! @attention	<BR>
//! @author		Y.Takeuchi
//! @date		07/03/22
//*******************************************************************
IW	_dvHdmiRxR8J66030FTConfig(void)
{
	IW ret = HDMIDRV_OK;
	return ret;
}

//*******************************************************************
//! @brief		R8J66030FT偺弶婜壔
//! @retval		張棟寢壥
//! @param		<BR>
//! @note		僨僶僀僗偺弶婜壔媦傃儗僕僗僞 儈儔乕儗僕僗僞偺弶婜愝掕
//!				傪峴偆<BR>
//! @attention	<BR>
//! @author		Y.Takeuchi
//! @date		07/03/23
//*******************************************************************
IW	_dvHdmiRxR8J66030FTReset(void)
{
	IW	ret = HDMIDRV_OK;
	UB	reg[4] = {0, 0, 0, 0};

	// 僜僼僩僂僃傾儕僙僢僩幚峴
	// General Control Register 0 (0x40)愝掕
	reg[0] = GENERAL_CONTROL_REG0_ADDR;
	reg[1] = SOFT_RST;

	ret = _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, 2, reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg0 = reg[1];
	} else {
		// 僜僼僩儕僙僢僩幐攕
		HdmiRxDrvErrCatch("Soft Reset On Fialed value:%x err:%d\n", reg[1], ret);
		return ret;
	}

	// 儈儔乕儗僕僗僞偺抣傪H/W儕僙僢僩屻偺忬懺偵栠偡
	memset(&gHdmiRxDrvR8J66030FTReg, 0x00, sizeof(gHdmiRxDrvR8J66030FTReg));
	gHdmiRxDrvR8J66030FTReg.StatusReg0 = 0x40;
	gHdmiRxDrvR8J66030FTReg.StatusReg1 = 0x04;
	gHdmiRxDrvR8J66030FTReg.GeneralControlReg4 = 0x02;
	gHdmiRxDrvR8J66030FTReg.GeneralControlReg6 = 0xE4;

	WAIT(IIC_WAIT_TIME);		// 擮偺偨傔10ms懸偪 T.B.D

	// 僜僼僩僂僃傾儕僙僢僩夝彍
	// General Control Register 0 (0x40)愝掕
	reg[0] = GENERAL_CONTROL_REG0_ADDR;
	reg[1] = gHdmiRxDrvR8J66030FTReg.GeneralControlReg0;
	reg[1] &= ~SOFT_RST;
	/* #HDCP_RESET3 ADD S 2007/11/29 Y.Takeuchi */
	//reg[1] |= DE_RST_EN;
	/* #HDCP_RESET3 ADD S 2007/11/29 Y.Takeuchi */
	ret = _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, 2, reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg0 = reg[1];
	} else {
		// 僜僼僩儕僙僢僩夝彍偵幐攕偟偨応崌偼偳偆偟傛偆傕側偄
		// 偙偺屻偺張棟偱奺儗僕僗僞偺弶婜愝掕傪峴偆偺偱張棟傪懕峴偡傞
		HdmiRxDrvErrCatch("Soft Reset Off Fialed value:%x err:%d\n", reg[1], ret);
	}

	WAIT(IIC_WAIT_TIME);		// 僶僗奐曻偺偨傔10ms懸偪 T.B.D

	// 奺儗僕僗僞偺弶婜愝掕 媦傃 儈儔乕儗僕僗僞偺愝掕
	// 妱崬傒儅僗僋儗僕僗僞(0x29)愝掕
	reg[0] = INTRUPT_ENABLE_REG_ADDR;
#ifdef HDMI_ASSP
	// ASSP 妱崬傒愝掕
	reg[1] = 0x7B;
	ret =  _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, 2, reg);
#else
	// C4US 撪憼IP 妱崬傒愝掕
	reg[1] = 0x00; 
	reg[2] = EXCP_F6 | EXCP_F4 | EXCP_F3 | EXCP_F2 | EXCP_F1;
	reg[3] = 0x00;
	ret =  _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, sizeof(reg), reg);
#endif
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.IntrMaskReg[0] = reg[1];
		gHdmiRxDrvR8J66030FTReg.IntrMaskReg[1] = reg[2];
		gHdmiRxDrvR8J66030FTReg.IntrMaskReg[2] = reg[3];
	} else {
		HdmiRxDrvErrCatch("Intrupt Reg Write Fialed value:%x err:%d\n", reg[1], ret);
	}

	WAIT(IIC_WAIT_TIME);		// 僶僗奐曻偺偨傔10ms懸偪 T.B.D

	// General Control Register 2 (0x42)愝掕
	reg[0] = GENERAL_CONTROL_REG2_ADDR;
	// 擖弌椡 YCbCr 4:22
	// Color Space 601
	// Pixel Reprication None
	reg[1] = OUT422 | IN422 | OUT_YCC | IN_YCC; 	// (0xF0)
	ret =  _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, 2, reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg2 = reg[1];
	} else {
		HdmiRxDrvErrCatch(" General Control Reg2 Write Fialed value:%x err:%d\n", reg[1], ret);
	}

	WAIT(IIC_WAIT_TIME);		// 僶僗奐曻偺偨傔10ms懸偪 T.B.D

	// General Control Register 3 (0x43)愝掕
	reg[0] = GENERAL_CONTROL_REG3_ADDR;
	// AV Mute愝掕
	reg[1] = AV_MUTE_SET;
	ret =  _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, 2, reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg3 = reg[1];
	} else {
		HdmiRxDrvErrCatch(" General Control Reg3 Write Fialed value:%x err:%d\n", reg[1], ret);
	}

	WAIT(IIC_WAIT_TIME);		// 僶僗奐曻偺偨傔10ms懸偪 T.B.D

	// General Control Register 4 (0x44)愝掕
	reg[0] = GENERAL_CONTROL_REG4_ADDR;
	// External Crystal 巊梡
	// 壒惡庬暿 Standard
	// 僒儞僾儕儞僌廃攇悢 庤摦愝掕
	// 僒儞僾儕儞僌廃攇悢 48 kHz
	reg[1] = X_POT | SF_MODE | SAMPLE_FREQ_48;		//(0x8A)
	ret =  _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, 2, reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg4 = reg[1];
	} else {
		HdmiRxDrvErrCatch(" General Control Reg4 Write Fialed value:%x err:%d\n", reg[1], ret);
	}

	WAIT(IIC_WAIT_TIME);		// 僶僗奐曻偺偨傔10ms懸偪 T.B.D

	// General Control Register 5 (0x45)愝掕
	reg[0] = GENERAL_CONTROL_REG5_ADDR;
	// IIS 僒儞僾儕儞僌僒僀僘 16bit
	// AMUTE_EN On Chip Audio Mute桳岠
	// 儅僗僞乕僋儘僢僋 256
	reg[1] = IIS_SS_32 | AMUTE_EN | MCLK_FREQ_256;					// (0x15)
	ret =  _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, 2, reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg5 = reg[1];
	} else {
		HdmiRxDrvErrCatch(" General Control Reg5 Write Fialed value:%x err:%d\n", reg[1], ret);
	}

	WAIT(IIC_WAIT_TIME);		// 僶僗奐曻偺偨傔10ms懸偪 T.B.D

	// General Control Register 8 (0x48)愝掕
	reg[0] = GENERAL_CONTROL_REG8_ADDR;
	reg[1] = 0x3C;	// T.B.D
	ret =  _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, 2, reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg8 = reg[1];
	} else {
		HdmiRxDrvErrCatch(" General Control Reg8 Write Fialed value:%x err:%d\n", reg[1], ret);
	}

	WAIT(IIC_WAIT_TIME);		// 僶僗奐曻偺偨傔10ms懸偪 T.B.D

	// Analog Test Register (0x49)愝掕
	reg[0] = ANALOG_TEST_REG_ADDR;
	reg[1] = 0x32;
	ret =  _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, 2, reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg9 = reg[1];
	} else {
		HdmiRxDrvErrCatch(" General Control Reg9 Write Fialed value:%x err:%d\n", reg[1], ret);
	}

	WAIT(IIC_WAIT_TIME);		// 僶僗奐曻偺偨傔10ms懸偪 T.B.D

	return ret;
}

//*******************************************************************
//! @brief		R8J66030FT偺擣徹弶婜壔
//! @retval		張棟寢壥
//! @param		<BR>
//! @note		<BR>
//! @attention	<BR>
//! @author		Y.Takeuchi
//! @date		07/03/22
//*******************************************************************
IW	_dvHdmiRxR8J66030FTHdcpReset(void)
{
	IW ret = HDMIDRV_OK;
	UB	reg[2] = {0, 0};

	// 僨僶僀僗揹尮抐
	ret = _dvHdmiRxR8J66030FTPowerDown();
	if (ret != HDMIDRV_OK) {
		HdmiRxDrvErrCatch("_dvHdmiRxR8J66030FTHdcpReset Err1 %d\n", ret);
		return ret;
	}

	// 10ms懸偪 T.B.D
	WAIT(300);

	// 擣徹儕僙僢僩幚峴
	// General Control Register 0 (0x40)愝掕
	reg[0] = GENERAL_CONTROL_REG0_ADDR;
	reg[1] = gHdmiRxDrvR8J66030FTReg.GeneralControlReg0;
	reg[1] |= HDCP_RST;
	ret = _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, sizeof(reg), reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg0 = reg[1];
	} else {
		HdmiRxDrvErrCatch("_dvHdmiRxR8J66030FTHdcpReset Err2 %d\n", ret);
		return ret;
	}

	// 10ms懸偪 T.B.D
	WAIT(IIC_WAIT_TIME);

	// 擣徹儕僙僢僩 揹尮OFF 夝彍
	reg[0] = GENERAL_CONTROL_REG0_ADDR;
	/* #HDCP_RESET3 CHG S 2007/11/29 Y.Takeuchi */
	//reg[1] &= ~PWR_DWN;
	//reg[1] &= ~HDCP_RST;
	reg[1] = 0;
	/* #HDCP_RESET3 CHG E 2007/11/29 Y.Takeuchi */
	ret = _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, sizeof(reg), reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg0 = reg[1];
	} else {
		HdmiRxDrvErrCatch("_dvHdmiRxR8J66030FTHdcpReset Err3 %d\n", ret);
		return ret;
	}

	return ret;
}

/* #HDCP_RESET2 ADD S 2007/11/12 Y.Takeuchi */
//*******************************************************************
//! @brief		R8J66030FT偺擣徹弶婜壔
//! @retval		張棟寢壥
//! @param		<BR>
//! @note		<BR>
//! @attention	<BR>
//! @author		Y.Takeuchi
//! @date		07/11/12
//*******************************************************************
IW	_dvHdmiRxR8J66030FTSoftReset(void)
{
	IW ret = HDMIDRV_OK;
	UB	reg[2] = {0, 0};

	// 僜僼僩儕僙僢僩幚峴
	// General Control Register 0 (0x40)愝掕
	reg[0] = GENERAL_CONTROL_REG0_ADDR;
	reg[1] = gHdmiRxDrvR8J66030FTReg.GeneralControlReg0;
	reg[1] |= SOFT_RST;
	ret = _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, sizeof(reg), reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg0 = reg[1];
	} else {
		HdmiRxDrvErrCatch("_dvHdmiRxR8J66030FTHdcpReset Err2 %d\n", ret);
		return ret;
	}

	// 10ms懸偪 T.B.D
	WAIT(IIC_WAIT_TIME);

	// 僜僼僩儕僙僢僩 夝彍
	reg[0] = GENERAL_CONTROL_REG0_ADDR;
	/* #HDCP_RESET3 CHG S 2007/11/29 Y.Takeuchi */
	//reg[1] &= ~SOFT_RST;
	reg[1] = 0;
	/* #HDCP_RESET3 CHG E 2007/11/29 Y.Takeuchi */
	ret = _HdmiRxDrvRegWrite(DV_HDMIRX_DEF_SLAVE_ADDR, sizeof(reg), reg);
	if (ret == HDMIDRV_OK) {
		gHdmiRxDrvR8J66030FTReg.GeneralControlReg0 = reg[1];
	} else {
		HdmiRxDrvErrCatch("_dvHdmiRxR8J66030FTHdcpReset Err3 %d\n", ret);
		return ret;
	}

	return ret;
}
/* #HDCP_RESET2 ADD E 2007/11/12 Y.Takeuchi */

//*******************************************************************
//! @brief		R8J66030FT偺妱崬傒儗儀儖愝掕
//! @retval		張棟寢壥
//! @param		<BR>
//! @note		<BR>
//! @attention	<BR>
//! @author		Y.Takeuchi
//! @date		07/04/24
//*******************************************************************
IW _dvHdmiRxR8J66030FTSetIntrlvl(UB ch, UB intr_lv)
{
	IW ret = HDMIDRV_OK;
#ifdef NOT_USE_INTR
	intr_lv = 0;
#endif
	// 妱崬傒儗儀儖偺愝掕
	ret = _dvIntcSetlvl(ch, intr_lv);
	return ret;
}

//*******************************************************************
//! @brief		R8J66030FT偺妱崬傒儅僗僋
//! @retval		張棟寢壥
//! @param		<BR>
//! @note		<BR>
//! @attention	<BR>
//! @author		Y.Takeuchi
//! @date		07/05/07
//*******************************************************************
IW _dvHdmiRxR8J66030FTSetIntrDisable()
{
	IW ret;
	UB reg[4] = {0, 0, 0, 0};