📄 lamp.map.rpt
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; -- 2 input functions ; 7 ;
; -- 1 input functions ; 15 ;
; -- 0 input functions ; 1 ;
; -- Combinational cells for routing ; 0 ;
; ; ;
; Logic elements by mode ; ;
; -- normal mode ; 96 ;
; -- arithmetic mode ; 0 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
; -- synchronous clear/load mode ; 1 ;
; -- asynchronous clear/load mode ; 31 ;
; ; ;
; Total registers ; 60 ;
; I/O pins ; 53 ;
; Maximum fan-out node ; clk ;
; Maximum fan-out ; 52 ;
; Total fan-out ; 457 ;
; Average fan-out ; 3.07 ;
+---------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
; |top1 ; 96 (1) ; 60 ; 0 ; 0 ; 53 ; 0 ; 36 (1) ; 9 (0) ; 51 (0) ; 0 (0) ; 0 (0) ; |top1 ;
; |led:cnt1| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; 0 (0) ; 0 (0) ; |top1|led:cnt1 ;
; |led:cnt2| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; 0 (0) ; 0 (0) ; |top1|led:cnt2 ;
; |led:cnt3| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; 0 (0) ; 0 (0) ; |top1|led:cnt3 ;
; |led:cnt4| ; 7 (7) ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 7 (7) ; 0 (0) ; 0 (0) ; |top1|led:cnt4 ;
; |top:v0| ; 67 (0) ; 32 ; 0 ; 0 ; 0 ; 0 ; 35 (0) ; 9 (0) ; 23 (0) ; 0 (0) ; 0 (0) ; |top1|top:v0 ;
; |cnt10de:u1| ; 8 (8) ; 5 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 2 (2) ; 3 (3) ; 0 (0) ; 0 (0) ; |top1|top:v0|cnt10de:u1 ;
; |cnt10de:u2| ; 7 (7) ; 4 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 (0) ; |top1|top:v0|cnt10de:u2 ;
; |cnt10de:u3| ; 8 (8) ; 5 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 2 (2) ; 3 (3) ; 0 (0) ; 0 (0) ; |top1|top:v0|cnt10de:u3 ;
; |cnt10de:u4| ; 7 (7) ; 4 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 1 (1) ; 3 (3) ; 0 (0) ; 0 (0) ; |top1|top:v0|cnt10de:u4 ;
; |contr:u0| ; 37 (37) ; 14 ; 0 ; 0 ; 0 ; 0 ; 23 (23) ; 3 (3) ; 11 (11) ; 0 (0) ; 0 (0) ; |top1|top:v0|contr:u0 ;
+----------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 60 ;
; Number of registers using Synchronous Clear ; 1 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 15 ;
; Number of registers using Asynchronous Load ; 16 ;
; Number of registers using Clock Enable ; 8 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; top:v0|contr:u0|light[2] ; 2 ;
; top:v0|contr:u0|light[3] ; 2 ;
; top:v0|contr:u0|qc[0] ; 16 ;
; top:v0|contr:u0|numm[5] ; 6 ;
; top:v0|contr:u0|numm[0] ; 2 ;
; top:v0|contr:u0|numm[2] ; 1 ;
; top:v0|cnt10de:u1|cout ; 4 ;
; top:v0|cnt10de:u3|cout ; 4 ;
; top:v0|contr:u0|numc[5] ; 2 ;
; Total number of inverted registers = 9 ; ;
+----------------------------------------+---------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
; 8:1 ; 3 bits ; 15 LEs ; 6 LEs ; 9 LEs ; Yes ; |top1|top:v0|contr:u0|light[0] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |top1|top:v0|cnt10de:u1|q[0] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |top1|top:v0|cnt10de:u2|q[0] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |top1|top:v0|cnt10de:u3|q[0] ;
; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |top1|top:v0|cnt10de:u4|q[0] ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------+
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
Info: Processing started: Mon Sep 08 18:51:58 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lamp -c lamp
Info: Found 1 design units, including 1 entities, in source file contr.v
Info: Found entity 1: contr
Info: Found 1 design units, including 1 entities, in source file cnt10de.v
Info: Found entity 1: cnt10de
Info: Found 1 design units, including 1 entities, in source file top1.v
Info: Found entity 1: top1
Info: Found 1 design units, including 1 entities, in source file Block1.bdf
Info: Found entity 1: Block1
Info: Found 1 design units, including 1 entities, in source file fre.v
Info: Found entity 1: fre
Info: Elaborating entity "top1" for the top level hierarchy
Warning: Using design file top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: top
Info: Elaborating entity "top" for hierarchy "top:v0"
Info: Elaborating entity "contr" for hierarchy "top:v0|contr:u0"
Warning (10036): Verilog HDL or VHDL warning at contr.v(10): object "m" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at contr.v(25): truncated value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at contr.v(31): truncated value with size 32 to match size of target (2)
Info: Elaborating entity "cnt10de" for hierarchy "top:v0|cnt10de:u1"
Warning (10230): Verilog HDL assignment warning at cnt10de.v(11): truncated value with size 32 to match size of target (4)
Warning: Using design file led.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: led
Info: Elaborating entity "led" for hierarchy "led:cnt1"
Info: Duplicate registers merged to single register
Info: Duplicate register "top:v0|contr:u0|numm[6]" merged to single register "top:v0|contr:u0|numm[7]"
Info: Duplicate register "top:v0|contr:u0|numm[4]" merged to single register "top:v0|contr:u0|numm[7]"
Info: Duplicate register "top:v0|contr:u0|numm[3]" merged to single register "top:v0|contr:u0|numm[7]"
Info: Duplicate register "top:v0|contr:u0|numm[1]" merged to single register "top:v0|contr:u0|numm[7]"
Info: Duplicate register "top:v0|contr:u0|numc[7]" merged to single register "top:v0|contr:u0|numm[7]"
Info: Duplicate register "top:v0|contr:u0|numc[6]" merged to single register "top:v0|contr:u0|numm[7]"
Info: Duplicate register "top:v0|contr:u0|numc[3]" merged to single register "top:v0|contr:u0|numm[7]"
Info: Duplicate register "top:v0|contr:u0|numc[1]" merged to single register "top:v0|contr:u0|numc[4]"
Info: Duplicate register "top:v0|contr:u0|numc[0]" merged to single register "top:v0|contr:u0|numm[2]"
Info: Duplicate register "top:v0|contr:u0|numc[2]" merged to single register "top:v0|contr:u0|numm[0]"
Warning: Reduced register "top:v0|contr:u0|numm[7]" with stuck data_in port to stuck value GND
Info: Registers with preset signals will power-up high
Info: Implemented 149 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 50 output pins
Info: Implemented 96 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings
Info: Processing ended: Mon Sep 08 18:52:30 2008
Info: Elapsed time: 00:00:34
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