lamp.tan.qmsg

交通灯。1）当乡村公路无车时

{ "Info" "ITDB_TH_RESULT" "top1:inst\|top:v0\|contr:u0\|numm\[2\] c clk_in -0.530 ns register " "Info: th for register \"top1:inst\|top:v0\|contr:u0\|numm\[2\]\" (data pin = \"c\", clock pin = \"clk_in\") is -0.530 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 7.363 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to destination register is 7.363 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_in 1 CLK PIN_28 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 26; CLK Node = 'clk_in'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/games/testlamp/Block1.bdf" { { 256 176 344 272 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fre:inst1\|clk 2 REG LC_X8_Y10_N1 52 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N1; Fanout = 52; REG Node = 'fre:inst1\|clk'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk_in fre:inst1|clk } "NODE_NAME" } } { "fre.v" "" { Text "D:/games/testlamp/fre.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.503 ns) + CELL(0.711 ns) 7.363 ns top1:inst\|top:v0\|contr:u0\|numm\[2\] 3 REG LC_X27_Y8_N8 1 " "Info: 3: + IC(3.503 ns) + CELL(0.711 ns) = 7.363 ns; Loc. = LC_X27_Y8_N8; Fanout = 1; REG Node = 'top1:inst\|top:v0\|contr:u0\|numm\[2\]'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "4.214 ns" { fre:inst1|clk top1:inst|top:v0|contr:u0|numm[2] } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.31 % ) " "Info: Total cell delay = 3.115 ns ( 42.31 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.248 ns ( 57.69 % ) " "Info: Total interconnect delay = 4.248 ns ( 57.69 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "7.363 ns" { clk_in fre:inst1|clk top1:inst|top:v0|contr:u0|numm[2] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "7.363 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|contr:u0|numm[2] } { 0.000ns 0.000ns 0.745ns 3.503ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" {  } { { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.908 ns - Shortest pin register " "Info: - Shortest pin to register delay is 7.908 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns c 1 PIN PIN_139 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_139; Fanout = 14; PIN Node = 'c'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "" { c } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/games/testlamp/Block1.bdf" { { 288 192 360 304 "c" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.961 ns) + CELL(0.478 ns) 7.908 ns top1:inst\|top:v0\|contr:u0\|numm\[2\] 2 REG LC_X27_Y8_N8 1 " "Info: 2: + IC(5.961 ns) + CELL(0.478 ns) = 7.908 ns; Loc. = LC_X27_Y8_N8; Fanout = 1; REG Node = 'top1:inst\|top:v0\|contr:u0\|numm\[2\]'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "6.439 ns" { c top1:inst|top:v0|contr:u0|numm[2] } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.947 ns ( 24.62 % ) " "Info: Total cell delay = 1.947 ns ( 24.62 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.961 ns ( 75.38 % ) " "Info: Total interconnect delay = 5.961 ns ( 75.38 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "7.908 ns" { c top1:inst|top:v0|contr:u0|numm[2] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "7.908 ns" { c c~out0 top1:inst|top:v0|contr:u0|numm[2] } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "7.363 ns" { clk_in fre:inst1|clk top1:inst|top:v0|contr:u0|numm[2] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "7.363 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|contr:u0|numm[2] } { 0.000ns 0.000ns 0.745ns 3.503ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "7.908 ns" { c top1:inst|top:v0|contr:u0|numm[2] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "7.908 ns" { c c~out0 top1:inst|top:v0|contr:u0|numm[2] } { 0.000ns 0.000ns 5.961ns } { 0.000ns 1.469ns 0.478ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 08 15:12:10 2008 " "Info: Processing ended: Mon Sep 08 15:12:10 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}