lamp.tan.qmsg

交通灯。1）当乡村公路无车时

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "3 " "Warning: Found 3 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "top1:inst\|top:v0\|cnt10de:u3\|cout " "Info: Detected ripple clock \"top1:inst\|top:v0\|cnt10de:u3\|cout\" as buffer" {  } { { "cnt10de.v" "" { Text "D:/games/testlamp/cnt10de.v" 5 -1 0 } } { "d:/program files/quartus/win/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/win/Assignment Editor.qase" 1 { { 0 "top1:inst\|top:v0\|cnt10de:u3\|cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "top1:inst\|top:v0\|cnt10de:u1\|cout " "Info: Detected ripple clock \"top1:inst\|top:v0\|cnt10de:u1\|cout\" as buffer" {  } { { "cnt10de.v" "" { Text "D:/games/testlamp/cnt10de.v" 5 -1 0 } } { "d:/program files/quartus/win/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/win/Assignment Editor.qase" 1 { { 0 "top1:inst\|top:v0\|cnt10de:u1\|cout" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "fre:inst1\|clk " "Info: Detected ripple clock \"fre:inst1\|clk\" as buffer" {  } { { "fre.v" "" { Text "D:/games/testlamp/fre.v" 3 -1 0 } } { "d:/program files/quartus/win/Assignment Editor.qase" "" { Assignment "d:/program files/quartus/win/Assignment Editor.qase" 1 { { 0 "fre:inst1\|clk" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_in register top1:inst\|top:v0\|cnt10de:u4\|q\[1\] register top1:inst\|top:v0\|contr:u0\|light\[5\] 47.89 MHz 20.882 ns Internal " "Info: Clock \"clk_in\" has Internal fmax of 47.89 MHz between source register \"top1:inst\|top:v0\|cnt10de:u4\|q\[1\]\" and destination register \"top1:inst\|top:v0\|contr:u0\|light\[5\]\" (period= 20.882 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.223 ns + Longest register register " "Info: + Longest register to register delay is 5.223 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns top1:inst\|top:v0\|cnt10de:u4\|q\[1\] 1 REG LC_X26_Y8_N1 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y8_N1; Fanout = 11; REG Node = 'top1:inst\|top:v0\|cnt10de:u4\|q\[1\]'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "" { top1:inst|top:v0|cnt10de:u4|q[1] } "NODE_NAME" } } { "cnt10de.v" "" { Text "D:/games/testlamp/cnt10de.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.775 ns) + CELL(0.590 ns) 1.365 ns top1:inst\|top:v0\|contr:u0\|Equal1~120 2 COMB LC_X27_Y8_N3 1 " "Info: 2: + IC(0.775 ns) + CELL(0.590 ns) = 1.365 ns; Loc. = LC_X27_Y8_N3; Fanout = 1; COMB Node = 'top1:inst\|top:v0\|contr:u0\|Equal1~120'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "1.365 ns" { top1:inst|top:v0|cnt10de:u4|q[1] top1:inst|top:v0|contr:u0|Equal1~120 } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 15 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.399 ns) + CELL(0.442 ns) 2.206 ns top1:inst\|top:v0\|contr:u0\|light\[5\]~1570 3 COMB LC_X27_Y8_N6 15 " "Info: 3: + IC(0.399 ns) + CELL(0.442 ns) = 2.206 ns; Loc. = LC_X27_Y8_N6; Fanout = 15; COMB Node = 'top1:inst\|top:v0\|contr:u0\|light\[5\]~1570'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "0.841 ns" { top1:inst|top:v0|contr:u0|Equal1~120 top1:inst|top:v0|contr:u0|light[5]~1570 } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.312 ns) + CELL(0.114 ns) 3.632 ns top1:inst\|top:v0\|contr:u0\|light\[5\]~1571 4 COMB LC_X27_Y9_N8 3 " "Info: 4: + IC(1.312 ns) + CELL(0.114 ns) = 3.632 ns; Loc. = LC_X27_Y9_N8; Fanout = 3; COMB Node = 'top1:inst\|top:v0\|contr:u0\|light\[5\]~1571'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "1.426 ns" { top1:inst|top:v0|contr:u0|light[5]~1570 top1:inst|top:v0|contr:u0|light[5]~1571 } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.867 ns) 5.223 ns top1:inst\|top:v0\|contr:u0\|light\[5\] 5 REG LC_X26_Y9_N1 1 " "Info: 5: + IC(0.724 ns) + CELL(0.867 ns) = 5.223 ns; Loc. = LC_X26_Y9_N1; Fanout = 1; REG Node = 'top1:inst\|top:v0\|contr:u0\|light\[5\]'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "1.591 ns" { top1:inst|top:v0|contr:u0|light[5]~1571 top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.013 ns ( 38.54 % ) " "Info: Total cell delay = 2.013 ns ( 38.54 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.210 ns ( 61.46 % ) " "Info: Total interconnect delay = 3.210 ns ( 61.46 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "5.223 ns" { top1:inst|top:v0|cnt10de:u4|q[1] top1:inst|top:v0|contr:u0|Equal1~120 top1:inst|top:v0|contr:u0|light[5]~1570 top1:inst|top:v0|contr:u0|light[5]~1571 top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "5.223 ns" { top1:inst|top:v0|cnt10de:u4|q[1] top1:inst|top:v0|contr:u0|Equal1~120 top1:inst|top:v0|contr:u0|light[5]~1570 top1:inst|top:v0|contr:u0|light[5]~1571 top1:inst|top:v0|contr:u0|light[5] } { 0.000ns 0.775ns 0.399ns 1.312ns 0.724ns } { 0.000ns 0.590ns 0.442ns 0.114ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.957 ns - Smallest " "Info: - Smallest clock skew is -4.957 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 7.357 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_in\" to destination register is 7.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_in 1 CLK PIN_28 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 26; CLK Node = 'clk_in'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/games/testlamp/Block1.bdf" { { 256 176 344 272 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fre:inst1\|clk 2 REG LC_X8_Y10_N1 52 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N1; Fanout = 52; REG Node = 'fre:inst1\|clk'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk_in fre:inst1|clk } "NODE_NAME" } } { "fre.v" "" { Text "D:/games/testlamp/fre.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.497 ns) + CELL(0.711 ns) 7.357 ns top1:inst\|top:v0\|contr:u0\|light\[5\] 3 REG LC_X26_Y9_N1 1 " "Info: 3: + IC(3.497 ns) + CELL(0.711 ns) = 7.357 ns; Loc. = LC_X26_Y9_N1; Fanout = 1; REG Node = 'top1:inst\|top:v0\|contr:u0\|light\[5\]'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "4.208 ns" { fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.34 % ) " "Info: Total cell delay = 3.115 ns ( 42.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.242 ns ( 57.66 % ) " "Info: Total interconnect delay = 4.242 ns ( 57.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "7.357 ns" { clk_in fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "7.357 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 12.314 ns - Longest register " "Info: - Longest clock path from clock \"clk_in\" to source register is 12.314 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_in 1 CLK PIN_28 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 26; CLK Node = 'clk_in'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/games/testlamp/Block1.bdf" { { 256 176 344 272 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fre:inst1\|clk 2 REG LC_X8_Y10_N1 52 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N1; Fanout = 52; REG Node = 'fre:inst1\|clk'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk_in fre:inst1|clk } "NODE_NAME" } } { "fre.v" "" { Text "D:/games/testlamp/fre.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.503 ns) + CELL(0.935 ns) 7.587 ns top1:inst\|top:v0\|cnt10de:u3\|cout 3 REG LC_X28_Y8_N2 4 " "Info: 3: + IC(3.503 ns) + CELL(0.935 ns) = 7.587 ns; Loc. = LC_X28_Y8_N2; Fanout = 4; REG Node = 'top1:inst\|top:v0\|cnt10de:u3\|cout'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "4.438 ns" { fre:inst1|clk top1:inst|top:v0|cnt10de:u3|cout } "NODE_NAME" } } { "cnt10de.v" "" { Text "D:/games/testlamp/cnt10de.v" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.016 ns) + CELL(0.711 ns) 12.314 ns top1:inst\|top:v0\|cnt10de:u4\|q\[1\] 4 REG LC_X26_Y8_N1 11 " "Info: 4: + IC(4.016 ns) + CELL(0.711 ns) = 12.314 ns; Loc. = LC_X26_Y8_N1; Fanout = 11; REG Node = 'top1:inst\|top:v0\|cnt10de:u4\|q\[1\]'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "4.727 ns" { top1:inst|top:v0|cnt10de:u3|cout top1:inst|top:v0|cnt10de:u4|q[1] } "NODE_NAME" } } { "cnt10de.v" "" { Text "D:/games/testlamp/cnt10de.v" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.050 ns ( 32.89 % ) " "Info: Total cell delay = 4.050 ns ( 32.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.264 ns ( 67.11 % ) " "Info: Total interconnect delay = 8.264 ns ( 67.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "12.314 ns" { clk_in fre:inst1|clk top1:inst|top:v0|cnt10de:u3|cout top1:inst|top:v0|cnt10de:u4|q[1] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "12.314 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|cnt10de:u3|cout top1:inst|top:v0|cnt10de:u4|q[1] } { 0.000ns 0.000ns 0.745ns 3.503ns 4.016ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "7.357 ns" { clk_in fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "7.357 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "12.314 ns" { clk_in fre:inst1|clk top1:inst|top:v0|cnt10de:u3|cout top1:inst|top:v0|cnt10de:u4|q[1] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "12.314 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|cnt10de:u3|cout top1:inst|top:v0|cnt10de:u4|q[1] } { 0.000ns 0.000ns 0.745ns 3.503ns 4.016ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "cnt10de.v" "" { Text "D:/games/testlamp/cnt10de.v" 10 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" {  } { { "cnt10de.v" "" { Text "D:/games/testlamp/cnt10de.v" 10 -1 0 } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "5.223 ns" { top1:inst|top:v0|cnt10de:u4|q[1] top1:inst|top:v0|contr:u0|Equal1~120 top1:inst|top:v0|contr:u0|light[5]~1570 top1:inst|top:v0|contr:u0|light[5]~1571 top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "5.223 ns" { top1:inst|top:v0|cnt10de:u4|q[1] top1:inst|top:v0|contr:u0|Equal1~120 top1:inst|top:v0|contr:u0|light[5]~1570 top1:inst|top:v0|contr:u0|light[5]~1571 top1:inst|top:v0|contr:u0|light[5] } { 0.000ns 0.775ns 0.399ns 1.312ns 0.724ns } { 0.000ns 0.590ns 0.442ns 0.114ns 0.867ns } } } { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "7.357 ns" { clk_in fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "7.357 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "12.314 ns" { clk_in fre:inst1|clk top1:inst|top:v0|cnt10de:u3|cout top1:inst|top:v0|cnt10de:u4|q[1] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "12.314 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|cnt10de:u3|cout top1:inst|top:v0|cnt10de:u4|q[1] } { 0.000ns 0.000ns 0.745ns 3.503ns 4.016ns } { 0.000ns 1.469ns 0.935ns 0.935ns 0.711ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_TSU_RESULT" "top1:inst\|top:v0\|contr:u0\|light\[5\] c clk_in 3.472 ns register " "Info: tsu for register \"top1:inst\|top:v0\|contr:u0\|light\[5\]\" (data pin = \"c\", clock pin = \"clk_in\") is 3.472 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "10.792 ns + Longest pin register " "Info: + Longest pin to register delay is 10.792 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns c 1 PIN PIN_139 14 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_139; Fanout = 14; PIN Node = 'c'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "" { c } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/games/testlamp/Block1.bdf" { { 288 192 360 304 "c" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.749 ns) + CELL(0.442 ns) 7.660 ns top1:inst\|top:v0\|contr:u0\|light\[5\]~1569 2 COMB LC_X26_Y8_N4 2 " "Info: 2: + IC(5.749 ns) + CELL(0.442 ns) = 7.660 ns; Loc. = LC_X26_Y8_N4; Fanout = 2; COMB Node = 'top1:inst\|top:v0\|contr:u0\|light\[5\]~1569'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "6.191 ns" { c top1:inst|top:v0|contr:u0|light[5]~1569 } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.249 ns) + CELL(0.292 ns) 9.201 ns top1:inst\|top:v0\|contr:u0\|light\[5\]~1571 3 COMB LC_X27_Y9_N8 3 " "Info: 3: + IC(1.249 ns) + CELL(0.292 ns) = 9.201 ns; Loc. = LC_X27_Y9_N8; Fanout = 3; COMB Node = 'top1:inst\|top:v0\|contr:u0\|light\[5\]~1571'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "1.541 ns" { top1:inst|top:v0|contr:u0|light[5]~1569 top1:inst|top:v0|contr:u0|light[5]~1571 } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.724 ns) + CELL(0.867 ns) 10.792 ns top1:inst\|top:v0\|contr:u0\|light\[5\] 4 REG LC_X26_Y9_N1 1 " "Info: 4: + IC(0.724 ns) + CELL(0.867 ns) = 10.792 ns; Loc. = LC_X26_Y9_N1; Fanout = 1; REG Node = 'top1:inst\|top:v0\|contr:u0\|light\[5\]'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "1.591 ns" { top1:inst|top:v0|contr:u0|light[5]~1571 top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.070 ns ( 28.45 % ) " "Info: Total cell delay = 3.070 ns ( 28.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.722 ns ( 71.55 % ) " "Info: Total interconnect delay = 7.722 ns ( 71.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "10.792 ns" { c top1:inst|top:v0|contr:u0|light[5]~1569 top1:inst|top:v0|contr:u0|light[5]~1571 top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "10.792 ns" { c c~out0 top1:inst|top:v0|contr:u0|light[5]~1569 top1:inst|top:v0|contr:u0|light[5]~1571 top1:inst|top:v0|contr:u0|light[5] } { 0.000ns 0.000ns 5.749ns 1.249ns 0.724ns } { 0.000ns 1.469ns 0.442ns 0.292ns 0.867ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" {  } { { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in destination 7.357 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_in\" to destination register is 7.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_in 1 CLK PIN_28 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 26; CLK Node = 'clk_in'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/games/testlamp/Block1.bdf" { { 256 176 344 272 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fre:inst1\|clk 2 REG LC_X8_Y10_N1 52 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N1; Fanout = 52; REG Node = 'fre:inst1\|clk'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk_in fre:inst1|clk } "NODE_NAME" } } { "fre.v" "" { Text "D:/games/testlamp/fre.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.497 ns) + CELL(0.711 ns) 7.357 ns top1:inst\|top:v0\|contr:u0\|light\[5\] 3 REG LC_X26_Y9_N1 1 " "Info: 3: + IC(3.497 ns) + CELL(0.711 ns) = 7.357 ns; Loc. = LC_X26_Y9_N1; Fanout = 1; REG Node = 'top1:inst\|top:v0\|contr:u0\|light\[5\]'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "4.208 ns" { fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.34 % ) " "Info: Total cell delay = 3.115 ns ( 42.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.242 ns ( 57.66 % ) " "Info: Total interconnect delay = 4.242 ns ( 57.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "7.357 ns" { clk_in fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "7.357 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "10.792 ns" { c top1:inst|top:v0|contr:u0|light[5]~1569 top1:inst|top:v0|contr:u0|light[5]~1571 top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "10.792 ns" { c c~out0 top1:inst|top:v0|contr:u0|light[5]~1569 top1:inst|top:v0|contr:u0|light[5]~1571 top1:inst|top:v0|contr:u0|light[5] } { 0.000ns 0.000ns 5.749ns 1.249ns 0.724ns } { 0.000ns 1.469ns 0.442ns 0.292ns 0.867ns } } } { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "7.357 ns" { clk_in fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "7.357 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk_in light\[5\] top1:inst\|top:v0\|contr:u0\|light\[5\] 14.077 ns register " "Info: tco from clock \"clk_in\" to destination pin \"light\[5\]\" through register \"top1:inst\|top:v0\|contr:u0\|light\[5\]\" is 14.077 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_in source 7.357 ns + Longest register " "Info: + Longest clock path from clock \"clk_in\" to source register is 7.357 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns clk_in 1 CLK PIN_28 26 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_28; Fanout = 26; CLK Node = 'clk_in'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "" { clk_in } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/games/testlamp/Block1.bdf" { { 256 176 344 272 "clk_in" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.745 ns) + CELL(0.935 ns) 3.149 ns fre:inst1\|clk 2 REG LC_X8_Y10_N1 52 " "Info: 2: + IC(0.745 ns) + CELL(0.935 ns) = 3.149 ns; Loc. = LC_X8_Y10_N1; Fanout = 52; REG Node = 'fre:inst1\|clk'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "1.680 ns" { clk_in fre:inst1|clk } "NODE_NAME" } } { "fre.v" "" { Text "D:/games/testlamp/fre.v" 3 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.497 ns) + CELL(0.711 ns) 7.357 ns top1:inst\|top:v0\|contr:u0\|light\[5\] 3 REG LC_X26_Y9_N1 1 " "Info: 3: + IC(3.497 ns) + CELL(0.711 ns) = 7.357 ns; Loc. = LC_X26_Y9_N1; Fanout = 1; REG Node = 'top1:inst\|top:v0\|contr:u0\|light\[5\]'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "4.208 ns" { fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.115 ns ( 42.34 % ) " "Info: Total cell delay = 3.115 ns ( 42.34 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.242 ns ( 57.66 % ) " "Info: Total interconnect delay = 4.242 ns ( 57.66 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "7.357 ns" { clk_in fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "7.357 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" {  } { { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.496 ns + Longest register pin " "Info: + Longest register to pin delay is 6.496 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns top1:inst\|top:v0\|contr:u0\|light\[5\] 1 REG LC_X26_Y9_N1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X26_Y9_N1; Fanout = 1; REG Node = 'top1:inst\|top:v0\|contr:u0\|light\[5\]'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "" { top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "contr.v" "" { Text "D:/games/testlamp/contr.v" 19 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.388 ns) + CELL(2.108 ns) 6.496 ns light\[5\] 2 PIN PIN_233 0 " "Info: 2: + IC(4.388 ns) + CELL(2.108 ns) = 6.496 ns; Loc. = PIN_233; Fanout = 0; PIN Node = 'light\[5\]'" {  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "6.496 ns" { top1:inst|top:v0|contr:u0|light[5] light[5] } "NODE_NAME" } } { "Block1.bdf" "" { Schematic "D:/games/testlamp/Block1.bdf" { { 264 784 960 280 "light\[5..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.108 ns ( 32.45 % ) " "Info: Total cell delay = 2.108 ns ( 32.45 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.388 ns ( 67.55 % ) " "Info: Total interconnect delay = 4.388 ns ( 67.55 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "6.496 ns" { top1:inst|top:v0|contr:u0|light[5] light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "6.496 ns" { top1:inst|top:v0|contr:u0|light[5] light[5] } { 0.000ns 4.388ns } { 0.000ns 2.108ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "7.357 ns" { clk_in fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "7.357 ns" { clk_in clk_in~out0 fre:inst1|clk top1:inst|top:v0|contr:u0|light[5] } { 0.000ns 0.000ns 0.745ns 3.497ns } { 0.000ns 1.469ns 0.935ns 0.711ns } } } { "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus/win/TimingClosureFloorplan.fld" "" "6.496 ns" { top1:inst|top:v0|contr:u0|light[5] light[5] } "NODE_NAME" } } { "d:/program files/quartus/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/program files/quartus/win/Technology_Viewer.qrui" "6.496 ns" { top1:inst|top:v0|contr:u0|light[5] light[5] } { 0.000ns 4.388ns } { 0.000ns 2.108ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}