lamp.map.qmsg

交通灯。1）当乡村公路无车时

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Sep 08 18:51:58 2008 " "Info: Processing started: Mon Sep 08 18:51:58 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off lamp -c lamp " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off lamp -c lamp" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "contr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file contr.v" { { "Info" "ISGN_ENTITY_NAME" "1 contr " "Info: Found entity 1: contr" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "cnt10de.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file cnt10de.v" { { "Info" "ISGN_ENTITY_NAME" "1 cnt10de " "Info: Found entity 1: cnt10de" {  } { { "cnt10de.v" "" { Text "G:/testlamp/cnt10de.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "top1.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file top1.v" { { "Info" "ISGN_ENTITY_NAME" "1 top1 " "Info: Found entity 1: top1" {  } { { "top1.v" "" { Text "G:/testlamp/top1.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Block1.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Block1.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Block1 " "Info: Found entity 1: Block1" {  } { { "Block1.bdf" "" { Schematic "G:/testlamp/Block1.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "fre.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file fre.v" { { "Info" "ISGN_ENTITY_NAME" "1 fre " "Info: Found entity 1: fre" {  } { { "fre.v" "" { Text "G:/testlamp/fre.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "top1 " "Info: Elaborating entity \"top1\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "top.v 1 1 " "Warning: Using design file top.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 top " "Info: Found entity 1: top" {  } { { "top.v" "" { Text "G:/testlamp/top.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "top top:v0 " "Info: Elaborating entity \"top\" for hierarchy \"top:v0\"" {  } { { "top1.v" "v0" { Text "G:/testlamp/top1.v" 6 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "contr top:v0\|contr:u0 " "Info: Elaborating entity \"contr\" for hierarchy \"top:v0\|contr:u0\"" {  } { { "top.v" "u0" { Text "G:/testlamp/top.v" 7 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "m contr.v(10) " "Warning (10036): Verilog HDL or VHDL warning at contr.v(10): object \"m\" assigned a value but never read" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 10 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 contr.v(25) " "Warning (10230): Verilog HDL assignment warning at contr.v(25): truncated value with size 32 to match size of target (2)" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 25 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 2 contr.v(31) " "Warning (10230): Verilog HDL assignment warning at contr.v(31): truncated value with size 32 to match size of target (2)" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 31 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cnt10de top:v0\|cnt10de:u1 " "Info: Elaborating entity \"cnt10de\" for hierarchy \"top:v0\|cnt10de:u1\"" {  } { { "top.v" "u1" { Text "G:/testlamp/top.v" 8 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 cnt10de.v(11) " "Warning (10230): Verilog HDL assignment warning at cnt10de.v(11): truncated value with size 32 to match size of target (4)" {  } { { "cnt10de.v" "" { Text "G:/testlamp/cnt10de.v" 11 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "led.v 1 1 " "Warning: Using design file led.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 led " "Info: Found entity 1: led" {  } { { "led.v" "" { Text "G:/testlamp/led.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led led:cnt1 " "Info: Elaborating entity \"led\" for hierarchy \"led:cnt1\"" {  } { { "top1.v" "cnt1" { Text "G:/testlamp/top1.v" 7 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "top:v0\|contr:u0\|numm\[6\] top:v0\|contr:u0\|numm\[7\] " "Info: Duplicate register \"top:v0\|contr:u0\|numm\[6\]\" merged to single register \"top:v0\|contr:u0\|numm\[7\]\"" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "top:v0\|contr:u0\|numm\[4\] top:v0\|contr:u0\|numm\[7\] " "Info: Duplicate register \"top:v0\|contr:u0\|numm\[4\]\" merged to single register \"top:v0\|contr:u0\|numm\[7\]\"" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "top:v0\|contr:u0\|numm\[3\] top:v0\|contr:u0\|numm\[7\] " "Info: Duplicate register \"top:v0\|contr:u0\|numm\[3\]\" merged to single register \"top:v0\|contr:u0\|numm\[7\]\"" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "top:v0\|contr:u0\|numm\[1\] top:v0\|contr:u0\|numm\[7\] " "Info: Duplicate register \"top:v0\|contr:u0\|numm\[1\]\" merged to single register \"top:v0\|contr:u0\|numm\[7\]\"" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "top:v0\|contr:u0\|numc\[7\] top:v0\|contr:u0\|numm\[7\] " "Info: Duplicate register \"top:v0\|contr:u0\|numc\[7\]\" merged to single register \"top:v0\|contr:u0\|numm\[7\]\"" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "top:v0\|contr:u0\|numc\[6\] top:v0\|contr:u0\|numm\[7\] " "Info: Duplicate register \"top:v0\|contr:u0\|numc\[6\]\" merged to single register \"top:v0\|contr:u0\|numm\[7\]\"" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "top:v0\|contr:u0\|numc\[3\] top:v0\|contr:u0\|numm\[7\] " "Info: Duplicate register \"top:v0\|contr:u0\|numc\[3\]\" merged to single register \"top:v0\|contr:u0\|numm\[7\]\"" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "top:v0\|contr:u0\|numc\[1\] top:v0\|contr:u0\|numc\[4\] " "Info: Duplicate register \"top:v0\|contr:u0\|numc\[1\]\" merged to single register \"top:v0\|contr:u0\|numc\[4\]\"" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "top:v0\|contr:u0\|numc\[0\] top:v0\|contr:u0\|numm\[2\] " "Info: Duplicate register \"top:v0\|contr:u0\|numc\[0\]\" merged to single register \"top:v0\|contr:u0\|numm\[2\]\"" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "top:v0\|contr:u0\|numc\[2\] top:v0\|contr:u0\|numm\[0\] " "Info: Duplicate register \"top:v0\|contr:u0\|numc\[2\]\" merged to single register \"top:v0\|contr:u0\|numm\[0\]\"" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "top:v0\|contr:u0\|numm\[7\] data_in GND " "Warning: Reduced register \"top:v0\|contr:u0\|numm\[7\]\" with stuck data_in port to stuck value GND" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } } { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } } { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } } { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } } { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } } { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } } { "cnt10de.v" "" { Text "G:/testlamp/cnt10de.v" 5 -1 0 } } { "cnt10de.v" "" { Text "G:/testlamp/cnt10de.v" 5 -1 0 } } { "contr.v" "" { Text "G:/testlamp/contr.v" 19 -1 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "149 " "Info: Implemented 149 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "3 " "Info: Implemented 3 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "50 " "Info: Implemented 50 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "96 " "Info: Implemented 96 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 7 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 7 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Sep 08 18:52:30 2008 " "Info: Processing ended: Mon Sep 08 18:52:30 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Info: Elapsed time: 00:00:34" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}