led.v

来自「交通灯。1）当乡村公路无车时」· Verilog 代码 · 共 22 行

module led(qout,clk,led);
input [3:0]qout;
input clk;
output [6:0]led;
reg [6:0]led;
always @(posedge clk)
begin
case(qout)
0:begin led=7'b0000001;end
1:begin led=7'b1001111;end
2:begin led=7'b0010010;end
3:begin led=7'b0000110;end
4:begin led=7'b1001100;end
5:begin led=7'b0100100;end
6:begin led=7'b0100000;end 
7:begin led=7'b0001111;end
8:begin led=7'b0000000;end
9:begin led=7'b0000100;end
default: begin led=7'b0000001;end
endcase
end
endmodule