📄 s608220v.src
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CP OutVoltValue+1,#out_135V_OPEN%256
JR ULT,change_to_wait_normal
delay_continue:
CP DelayTimeCnt,#0
JR NE,end_CasePRO_DELAY
CP OutVoltValue,#OUT_180V/256
JR UGT,GO_disp_TURN_NORMAL
JR ULT,GO_disp_TURN_low
CP OutVoltValue+1,#OUT_180V%256
JR UGT,GO_disp_TURN_NORMAL
GO_disp_TURN_low:
RL1 ON
WORK_LED ON
DELAY_LED OFF
ERROR_LED ON
LD R6,DispOutVolt
LD R7,DispOutVolt+1
CALL BCD_conversion
CALL set_display_data
LD R0,#250
GOTO_aaww:
NOP
DEC R0
CP R0,#0
JR NE,GOTO_aaww
LD ProtectStatus,#PRO_100
LD DispStatus,#DISP_INLOW
JR end_CasePRO_DELAY
GO_disp_TURN_NORMAL:
LD ProtectStatus,#PRO_NORMAL
RL1 ON
LD DispStatus,#DISP_NORMAL
JR end_CasePRO_DELAY
change_to_wait_normal:
LD ProtectStatus,#PRO_ACTIVE
end_CasePRO_DELAY:
RET
;-----------------------------------------------------
CasePRO_WAITNORMAL:
CP OutVoltValue,#out_135V_OPEN/256
JR ULT,set_disp_low
JR UGT,dete_high
CP OutVoltValue+1,#out_135V_OPEN%256
JR UGT,dete_high
set_disp_low:
LD DispStatus,#DISP_INLOW
JR end_CasePRO_WAITNORMAL
dete_high:
CP OutVoltValue,#(OUT_255V-5)/256
JR ULT,change_to_pro_delay
JR UGT,set_disp_high
CP OutVoltValue+1,#(OUT_255V-5)%256
JR ULT,change_to_pro_delay
set_disp_high:
LD DispStatus,#DISP_OUTHIGH
JR end_CasePRO_WAITNORMAL
change_to_pro_delay:
LD ProtectStatus,#PRO_DELAY
LD DispStatus,#DISP_DELAY_TIME
reset_delay_time:
TM FlagReg,#delay_short_long_flag
JR NZ,set_long_delay_time
LD DelayTimeCnt,#_5sec
JR end_CasePRO_WAITNORMAL
set_long_delay_time:
LD DelayTimeCnt,#_120sec
end_CasePRO_WAITNORMAL:
RET
DELAY_relay: .MACRO
CLR R0
DELAY_to:
NOP
NOP
NOP
INC R0
CP R0,#0A0H
JR NE,DELAY_to
.ENDM
;输入电压范围编码:
OUTPUT_SEG0: .EQU 0*3
OUTPUT_SEG1: .EQU 1*3
OUTPUT_SEG2: .EQU 2*3
OUTPUT_SEG3: .EQU 3*3
OUTPUT_SEG4: .EQU 4*3
OUTPUT_SEG5: .EQU 5*3
OUTPUT_SEG6: .EQU 6*3
OUTPUT_SEG7: .EQU 7*3
OutputStatus: .RAM_DS 1
regulate_output:: ;;调压执行程序
JP regelate_method0 ;输入电压<151
JP regelate_method1 ; <166
JP regelate_method2 ; <177
JP regelate_method3 ; <195
JP regelate_method4 ; <204
JP regelate_method5 ; <224
JP regelate_method6 ; <231
JP regelate_method7 ; >=231
regelate_method0:
RL2 OFF
DELAY_relay
RL3 ON
DELAY_relay
RL4 OFF
JP end_regulate_output
regelate_method1:
RL2 ON
DELAY_relay
RL3 ON
DELAY_relay
RL4 OFF
JP end_regulate_output
regelate_method2:
RL2 OFF
DELAY_relay
RL3 ON
DELAY_relay
RL4 ON
JP end_regulate_output
regelate_method3:
RL2 ON
DELAY_relay
RL3 ON
DELAY_relay
RL4 ON
JP end_regulate_output
regelate_method4:
RL2 OFF
DELAY_relay
RL3 OFF
DELAY_relay
RL4 OFF
JP end_regulate_output
regelate_method5:
RL2 ON
DELAY_relay
RL3 OFF
DELAY_relay
RL4 OFF
JP end_regulate_output
regelate_method6:
RL2 OFF
DELAY_relay
RL3 OFF
DELAY_relay
RL4 ON
JP end_regulate_output
regelate_method7:
RL2 ON
DELAY_relay
RL3 OFF
DELAY_relay
RL4 ON
end_regulate_output:
idle_routine::
LD R1,#2
_idle_loop:
OFF_DISP
IDLE
OFF_DISP
DEC R1
JR NZ,_idle_loop
RET
;-------------------------------------------------
CJRR0ULT:
CP R0,R2
JP ULT,ULTaddr
JP UGT,ULTend_cmp_
CP R1,R3
JP ULT,ULTaddr
ULTend_cmp_:
LD R4,#00H
RET
ULTaddr:
LD R4,#0ffH
RET
CJRR0UGT:
CP R0,R2
JP UGT,UGTaddr
JP ULT,UGTend_cmp_
CP R1,R3
JP UGT,UGTaddr
UGTend_cmp_:
LD R5,#00H
RET
UGTaddr:
LD R5,#0ffH
RET
;检查输入电压范围
; R7:返回输入电压范围编码
IN_151: .EQU 151
IN_145: .EQU 145
IN_166: .EQU 166
IN_154: .EQU 154
IN_177: .EQU 177
IN_170: .EQU 170
IN_195: .EQU 195
IN_178: .EQU 178
IN_204: .EQU 204
IN_196: .EQU 196
IN_224: .EQU 224
IN_201: .EQU 201
IN_231: .EQU 231
IN_221: .EQU 221
regulate_set_output_status::
LD R7,OutputStatus
CLR R6
ADD R7,#IIIIIIIII%256
ADC R6,#IIIIIIIII/256
JP @RR6
IIIIIIIII:
JP OUT_0
JP OUT_1
JP OUT_2
JP OUT_3
JP OUT_4
JP OUT_5
JP OUT_6
JP OUT_7
;-----------------------
OUT_0:
LD R2,#IN_151/256
LD R3,#IN_151%256
CALL CJRR0ULT
CP R4,#0ffH
JP EQ,set_input_seg0
;-------
Cmp_HighVolt:
LD R2,#IN_231/256
LD R3,#IN_231%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,set_input_seg7
CP OutputStatus,#15
JP EQ,No_Change_OUT5h
;--------
LD R2,#IN_221/256
LD R3,#IN_221%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,set_input_seg6
CP OutputStatus,#12
JP EQ,No_Change_OUT4h
;-------
LD R2,#IN_204/256
LD R3,#IN_204%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,set_input_seg5
CP OutputStatus,#9
JP EQ,No_Change_OUT3h
;-------
LD R2,#IN_195/256
LD R3,#IN_195%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,set_input_seg4
CP OutputStatus,#6
JP EQ,No_Change_OUT2h
;-------
LD R2,#IN_177/256
LD R3,#IN_177%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,set_input_seg3
CP OutputStatus,#3
JP EQ,No_Change_OUT1h
;-------
LD R2,#IN_166/256
LD R3,#IN_166%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,set_input_seg2
;-------
JP set_input_seg1
;-------------
OUT_1:
LD R2,#IN_166/256
LD R3,#IN_166%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,great_change_1
;===----
LD R2,#IN_145/256
LD R3,#IN_145%256
CALL CJRR0ULT
CP R4,#0ffH
JP EQ,set_input_seg0
;---------
JP set_input_seg1
;----------------
great_change_1:
JP Cmp_HighVolt
No_Change_OUT1h:
JP set_input_seg2
;-------------
OUT_2:
LD R2,#IN_177/256
LD R3,#IN_177%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,great_change_2
;===----
LD R2,#IN_154/256
LD R3,#IN_154%256
CALL CJRR0ULT
CP R4,#0ffH
JP EQ,less_change_2
;-------
JP set_input_seg2
less_change_2:
JP Cmp_LowVolt
No_Change_OUT2l:
JP set_input_seg1
;--------
great_change_2:
JP Cmp_HighVolt
No_Change_OUT2h:
JP set_input_seg3
;-------------
OUT_3:
LD R2,#IN_195/256
LD R3,#IN_195%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,great_change_3
;====------
LD R2,#IN_170/256
LD R3,#IN_170%256
CALL CJRR0ULT
CP R4,#0ffH
JP EQ,less_change_3
;===--------
JP set_input_seg3
great_change_3:
JP Cmp_HighVolt
No_Change_OUT3h:
JP set_input_seg4
;-----------
less_change_3:
JP Cmp_LowVolt
No_Change_OUT3l:
JP set_input_seg2
;-------------
OUT_4:
TM DELAY_300_display_flag,#10H
JR Z,GO_do
LD GO_do_time,#2
GO_do:
LD R2,#IN_204/256
LD R3,#IN_204%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,great_chang_4
;===----
JP Cmp_LowVolt
No_Change_OUT4l:
JP set_input_seg4
;-----
great_chang_4:
JP Cmp_HighVolt
No_Change_OUT4h:
JP set_input_seg5
;-------------
OUT_5:
LD R2,#IN_224/256
LD R3,#IN_224%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,great_chang_5
;===----
JP Cmp_LowVolt
No_Change_OUT5l:
JP set_input_seg5
;--
great_chang_5:
JP Cmp_HighVolt
No_Change_OUT5h:
JP set_input_seg6
;-------------
OUT_6:
LD R2,#IN_231/256
LD R3,#IN_231%256
CALL CJRR0UGT
CP R5,#0ffH
JP EQ,set_input_seg7
JP Cmp_LowVolt
;------
No_Change_OUT6:
JP set_input_seg6
;-------------
OUT_7:
Cmp_LowVolt:
LD R2,#IN_145/256
LD R3,#IN_145%256
CALL CJRR0ULT
CP R4,#0ffH
JP EQ,set_input_seg0
CP OutputStatus,#6
JP EQ,No_Change_OUT2l
;-------
LD R2,#IN_154/256
LD R3,#IN_154%256
CALL CJRR0ULT
CP R4,#0ffH
JP EQ,set_input_seg1
CP OutputStatus,#9
JP EQ,No_Change_OUT3l
;-------
LD R2,#IN_170/256
LD R3,#IN_170%256
CALL CJRR0ULT
CP R4,#0ffH
JP EQ,set_input_seg2
;-------
LD R2,#IN_178/256
LD R3,#IN_178%256
CALL CJRR0ULT
CP R4,#0ffH
JP EQ,set_input_seg3
CP OutputStatus,#12
JP EQ,No_Change_OUT4l
;-------
LD R2,#IN_196/256
LD R3,#IN_196%256
CALL CJRR0ULT
CP R4,#0ffH
JP EQ,set_input_seg4
CP OutputStatus,#15
JP EQ,No_Change_OUT5l
;-------
LD R2,#IN_201/256
LD R3,#IN_201%256
CALL CJRR0ULT
CP R4,#0ffH
JP EQ,set_input_seg5
CP OutputStatus,#18
JP EQ,No_Change_OUT6
;-------
LD R2,#IN_221/256
LD R3,#IN_221%256
CALL CJRR0ULT
CP R4,#0ffH
JP EQ,set_input_seg6
;-------
JP set_input_seg7
;-------------
set_input_seg0:
LD R7,#OUTPUT_SEG0
RET
set_input_seg1:
LD R7,#OUTPUT_SEG1
RET
set_input_seg2:
LD R7,#OUTPUT_SEG2
RET
set_input_seg3:
LD R7,#OUTPUT_SEG3
RET
set_input_seg4:
LD R7,#OUTPUT_SEG4
RET
set_input_seg5:
LD R7,#OUTPUT_SEG5
RET
set_input_seg6:
LD R7,#OUTPUT_SEG6
RET
set_input_seg7:
LD R7,#OUTPUT_SEG7
RET
;-------------------------------------------------
regulate_deal::
CALL regulate_set_output_status
CP R7,OutputStatus
JR EQ,cant_regulate
LD OutputStatus,R7
CLR R6
ADD R7,#regulate_output%256
ADC R6,#regulate_output/256
CALL @RR6
AND UserFlag,#~ProtectEable
AND FlagReg,#~FreshDisp
CALL deal_input
RET
cant_regulate:
OR UserFlag,#ProtectEable
RET
;================================================
init_parameter::
LD DispStatus,#DISP_DELAY_TIME
LD KeyStatus,#Key_normal
LD ProtectStatus,#PRO_ACTIVE
LD SumOutCnt,#8
WORK_LED OFF
DELAY_LED ON
ERROR_LED OFF
AND FlagReg,#~IN_OUT_Volt_flag
AND FlagReg,#~DispUnchange
LD SystemTime,#SYS_TIME
LD Cnt1000ms,#_1000ms
LD Cnt500ms,#ms500
TM FlagReg,#delay_short_long_flag
JR Z,clr_otherflag_delay
OR UserFlag,#delay_set_bak
JR skip_low
clr_otherflag_delay:
AND UserFlag,#~delay_set_bak
skip_low:
CALL reset_delay_time
OR delaydeal_f,#80H
RET
.END
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