spce3200_constant.h

GPRS模组资料包含DEMO

#define C_TMB_TMB1_256HZ          0x00080000    // P_TMB_MODE_CTRL
#define C_TMB_TMB1_512HZ          0x00090000    // P_TMB_MODE_CTRL
#define C_TMB_TMB1_1024HZ         0x000a0000    // P_TMB_MODE_CTRL
#define C_TMB_TMB1_2048HZ         0x000b0000    // P_TMB_MODE_CTRL
#define C_TMB_TMB1_EN             0x00800000    // P_TMB_MODE_CTRL

#define C_TMB_TMB0_1HZ            0x00000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_2HZ            0x01000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_4HZ            0x02000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_8HZ            0x03000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_16HZ           0x04000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_32HZ           0x05000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_64HZ           0x06000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_128HZ          0x07000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_256HZ          0x08000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_512HZ          0x09000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_1024HZ         0x0a000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_2048HZ         0x0b000000    // P_TMB_MODE_CTRL
#define C_TMB_TMB0_EN             0x80000000    // P_TMB_MODE_CTRL

#define C_TMB_TMB2_INTEN          0x00400000    // P_TMB_INT_STATUS
#define C_TMB_TMB2_FLAG           0x00800000    // P_TMB_INT_STATUS
#define C_TMB_TMB1_INTEN          0x04000000    // P_TMB_INT_STATUS
#define C_TMB_TMB1_FLAG           0x08000000    // P_TMB_INT_STATUS
#define C_TMB_TMB0_INTEN          0x40000000    // P_TMB_INT_STATUS
#define C_TMB_TMB0_FLAG           0x80000000    // P_TMB_INT_STATUS

#define C_TMB_RST_COMMAND         0x50000005    // P_TMB_RESET_COMMAND

//******************************************************************//
//                              UART                                //
//******************************************************************//

#define C_UART_CLK_EN             0x00000001    // P_UART_CLK_CONF
#define C_UART_RST_DIS            0x00000002    // P_UART_CLK_CONF

#define C_UART_PORT_SEL           0x01000000    // P_UART_INTERFACE_SEL

#define C_UART_SEND_BREAK         0x00000001    // P_UART_MODE_CTRL
#define C_UART_NO_PARITY          0x00000000    // P_UART_MODE_CTRL
#define C_UART_ODD_PARITY         0x00000002    // P_UART_MODE_CTRL
#define C_UART_EVEN_PARITY        0x00000006    // P_UART_MODE_CTRL
#define C_UART_STOP_1BIT          0x00000000    // P_UART_MODE_CTRL
#define C_UART_STOP_2BIT          0x00000008    // P_UART_MODE_CTRL
#define C_UART_FIFO_EN            0x00000010    // P_UART_MODE_CTRL
#define C_UART_DATA_5BIT          0x00000000    // P_UART_MODE_CTRL
#define C_UART_DATA_6BIT          0x00000020    // P_UART_MODE_CTRL
#define C_UART_DATA_7BIT          0x00000040    // P_UART_MODE_CTRL
#define C_UART_DATA_8BIT          0x00000060    // P_UART_MODE_CTRL
#define C_UART_CTRL_EN            0x00001000    // P_UART_MODE_CTRL
#define C_UART_TIMEOUT_INTEN      0x00002000    // P_UART_MODE_CTRL
#define C_UART_TX_INTEN           0x00004000    // P_UART_MODE_CTRL
#define C_UART_RX_INTEN           0x00008000    // P_UART_MODE_CTRL

#define C_UART_BUSY_FLAG          0x00000008    // P_UART_TXRX_STATUS
#define C_UART_RXFIFO_EMPTY       0x00000010    // P_UART_TXRX_STATUS
#define C_UART_TXFIFO_FULL        0x00000020    // P_UART_TXRX_STATUS
#define C_UART_RXFIFO_FULL        0x00000040    // P_UART_TXRX_STATUS
#define C_UART_TXFIFO_EMPTY       0x00000080    // P_UART_TXRX_STATUS
#define C_UART_TIMEOUT_FLAG       0x00002000    // P_UART_TXRX_STATUS
#define C_UART_TX_FLAG            0x00004000    // P_UART_TXRX_STATUS
#define C_UART_RX_FLAG            0x00008000    // P_UART_TXRX_STATUS

#define C_UART_FRAME_ERR          0x00000001    // P_UART_ERR_STATUS
#define C_UART_PARITY_ERR         0x00000002    // P_UART_ERR_STATUS
#define C_UART_BREAK_ERR          0x00000004    // P_UART_ERR_STATUS
#define C_UART_RXFIFOOV_ERR       0x00000008    // P_UART_ERR_STATUS
#define C_UART_RX_SIGNAL          0x00008000    // P_UART_ERR_STATUS

#define C_UART_WAKEUP_FLAG        0x00000002    // P_UART_WAKEUP_STATUS

//******************************************************************//
//                              SPI                                 //
//******************************************************************//

#define C_SPI_CLK_EN              0x00000001    // P_SPI_CLK_CONF
#define C_SPI_RST_DIS             0x00000002    // P_SPI_CLK_CONF

#define C_SPI_PORT_SEL            0x00000100    // P_SPI_INTERFACE_SEL

#define C_SPI_CLK_27MDIV2         0x00000000    // P_SPI_MODE_CTRL
#define C_SPI_CLK_27MDIV4         0x00000001    // P_SPI_MODE_CTRL
#define C_SPI_CLK_27MDIV8         0x00000002    // P_SPI_MODE_CTRL
#define C_SPI_CLK_27MDIV16        0x00000003    // P_SPI_MODE_CTRL
#define C_SPI_CLK_27MDIV32        0x00000004    // P_SPI_MODE_CTRL
#define C_SPI_CLK_27MDIV64        0x00000005    // P_SPI_MODE_CTRL
#define C_SPI_CLK_27MDIV128       0x00000006    // P_SPI_MODE_CTRL

#define C_SPI_SPO_HIGH            0x00000000    // P_SPI_MODE_CTRL
#define C_SPI_SPO_LOW             0x00000040    // P_SPI_MODE_CTRL
#define C_SPI_SPH_0               0x00000000    // P_SPI_MODE_CTRL
#define C_SPI_SPH_180             0x00000080    // P_SPI_MODE_CTRL
#define C_SPI_MASTER_MODE         0x00000000    // P_SPI_MODE_CTRL
#define C_SPI_SLAVE_MODE          0x02000000    // P_SPI_MODE_CTRL
#define C_SPI_SOFT_RST            0x04000000    // P_SPI_MODE_CTRL
#define C_SPI_TEST_MODE           0x08000000    // P_SPI_MODE_CTRL
#define C_SPI_NORMAL_MODE         0x00000000    // P_SPI_MODE_CTRL
#define C_SPI_CTRL_EN             0x80000000    // P_SPI_MODE_CTRL

#define C_SPI_TX_INTEN            0x40000000    // P_SPI_TX_STATUS
#define C_SPI_TX_FLAG             0x80000000    // P_SPI_TX_STATUS

#define C_SPI_RXOV_FLAG           0x04000000    // P_SPI_RX_STATUS
#define C_SPI_RX_INTEN            0x40000000    // P_SPI_RX_STATUS
#define C_SPI_RX_FLAG             0x80000000    // P_SPI_RX_STATUS

#define C_SPI_TXFIFO_EMPTY        0x00000001    // P_SPI_TXRX_STATUS
#define C_SPI_TXFIFO_NOTFULL      0x00000002    // P_SPI_TXRX_STATUS
#define C_SPI_RXFIFO_NOTEMPTY     0x00000004    // P_SPI_TXRX_STATUS
#define C_SPI_RXFIFO_FULL         0x00000008    // P_SPI_TXRX_STATUS
#define C_SPI_BUSY_FLAG           0x00000010    // P_SPI_TXRX_STATUS
#define C_SPI_AUTO_CLR            0x40000000    // P_SPI_TXRX_STATUS
#define C_SPI_MANNUAL_CLR         0x00000000    // P_SPI_TXRX_STATUS
#define C_SPI_OV_SKIP             0x00000000    // P_SPI_TXRX_STATUS
#define C_SPI_OV_OVERWRITE        0x80000000    // P_SPI_TXRX_STATUS

//******************************************************************//
//                              I2C                                 //
//******************************************************************//

#define C_I2C_CLK_EN              0x00000001    // P_I2C_CLK_CONF
#define C_I2C_RST_DIS             0x00000002    // P_I2C_CLK_CONF

#define C_I2C_PORT_SEL            0x00000001    // P_I2C_INTERFACE_SEL

#define C_I2C_8BIT_START          0x00000001    // P_I2C_MODE_CTRL
#define C_I2C_16BIT_START         0x00000002    // P_I2C_MODE_CTRL
#define C_I2C_8NBIT_START         0x00000004    // P_I2C_MODE_CTRL
#define C_I2C_8BIT_ACK            0x00000008    // P_I2C_MODE_CTRL
#define C_I2C_16BIT_ACK           0x00000010    // P_I2C_MODE_CTRL
#define C_I2C_8NBIT_ACK           0x00000020    // P_I2C_MODE_CTRL
#define C_I2C_TX_MODE             0x00000000    // P_I2C_MODE_CTRL
#define C_I2C_RX_MODE             0x00000040    // P_I2C_MODE_CTRL
#define C_I2C_END_NAK             0x00000000    // P_I2C_MODE_CTRL
#define C_I2C_END_ACK             0x00000080    // P_I2C_MODE_CTRL
#define C_I2C_8NBIT_STOP          0x00000100    // P_I2C_MODE_CTRL

#define C_I2C_INT_EN              0x00000002    // P_I2C_INT_STATUS
#define C_I2C_INT_FLAG            0x00000001    // P_I2C_INT_STATUS

//******************************************************************//
//                                SIO                               //
//******************************************************************//

#define C_JTAG_PORT_SEL           0x00000000    // P_SIO_INTERFACE_SEL
#define C_SIO_PORT_SEL            0x00000100    // P_SIO_INTERFACE_SEL

#define C_SIO_CLK_EN              0x00000001    // P_SIO_CLK_CONF
#define C_SIO_RST_DIS             0x00000002    // P_SIO_CLK_CONF

#define C_SIO_TXRX_STOP           0x00000000    // P_SIO_MODE_CTRL
#define C_SIO_TXRX_START          0x00000001    // P_SIO_MODE_CTRL
#define C_SIO_READ_MODE           0x00000000    // P_SIO_MODE_CTRL
#define C_SIO_WRITE_MODE          0x00000002    // P_SIO_MODE_CTRL
#define C_SIO_MSB_FIRST           0x00000000    // P_SIO_MODE_CTRL
#define C_SIO_LSB_FIRST           0x00000004    // P_SIO_MODE_CTRL
#define C_SIO_INT_CLR             0x00000080    // P_SIO_MODE_CTRL
#define C_SIO_ADDR_16BIT          0x00000000    // P_SIO_MODE_CTRL
#define C_SIO_ADDR_NONE           0x00000100    // P_SIO_MODE_CTRL
#define C_SIO_ADDR_8BIT           0x00000200    // P_SIO_MODE_CTRL
#define C_SIO_ADDR_24BIT          0x00000300    // P_SIO_MODE_CTRL
#define C_SIO_CLK_27MDIV16        0x00000000    // P_SIO_MODE_CTRL
#define C_SIO_CLK_27MDIV4         0x00000400    // P_SIO_MODE_CTRL
#define C_SIO_CLK_27MDIV8         0x00000800    // P_SIO_MODE_CTRL
#define C_SIO_CLK_27MDIV32        0x00000C00    // P_SIO_MODE_CTRL
#define C_SIO_RWBIT_NORMAL        0x00000000    // P_SIO_MODE_CTRL
#define C_SIO_RWBIT_LOW           0x00001000    // P_SIO_MODE_CTRL
#define C_SIO_INT_EN              0x00002000    // P_SIO_MODE_CTRL
#define C_SIO_DMA_EN              0x00004000    // P_SIO_MODE_CTRL
#define C_SIO_DATA_8BIT           0x00000000    // P_SIO_MODE_CTRL
#define C_SIO_DATA_16BIT          0x00008000    // P_SIO_MODE_CTRL
#define C_SIO_INT_FLAG            0x40000000    // P_SIO_MODE_CTRL
#define C_SIO_DATA_REQ            0x80000000    // P_SIO_MODE_CTRL

#define C_SIO_TX_MANUAL           0x00000000    // P_SIO_AUTO_CTRL
#define C_SIO_TX_AUTO             0x00000001    // P_SIO_AUTO_CTRL
#define C_SIO_RDYPIN_DETECT       0x00000002    // P_SIO_AUTO_CTRL

//******************************************************************//
//                             NAND                                 //
//******************************************************************//

#define C_NAND_PORT_SEL           0x00000001    // P_NAND_INTERFACE_SEL

#define C_NAND_CLK_EN             0x00000001    // P_NAND_CLK_CONF
#define C_NAND_RST_DIS            0x00000002    // P_NAND_CLK_CONF

#define C_NAND_PORT_EN            0x00000001    // P_NAND_MODE_CTRL
#define C_NAND_CEN_LOW            0x00000000    // P_NAND_MODE_CTRL
#define C_NAND_CEN_HIGH           0x00000002    // P_NAND_MODE_CTRL
#define C_NAND_WPN_LOW            0x00000000    // P_NAND_MODE_CTRL
#define C_NAND_WPN_HIGH           0x00000004    // P_NAND_MODE_CTRL
#define C_NAND_CMD_READ           0x00000000    // P_NAND_MODE_CTRL
#define C_NAND_CMD_WRITE          0x00000008    // P_NAND_MODE_CTRL
#define C_NAND_RDY_RISE           0x00000000    // P_NAND_MODE_CTRL
#define C_NAND_CLE_FALL           0x00000010    // P_NAND_MODE_CTRL
#define C_NAND_ALE_FALL           0x00000020    // P_NAND_MODE_CTRL
#define C_NAND_RD_RESV            0x00000030    // P_NAND_MODE_CTRL
#define C_NAND_ALE_1CYCLE         0x00000000    // P_NAND_MODE_CTRL
#define C_NAND_ALE_2CYCLE         0x00000040    // P_NAND_MODE_CTRL
#define C_NAND_ALE_3CYCLE         0x00000080    // P_NAND_MODE_CTRL
#define C_NAND_ALE_4CYCLE         0x000000C0    // P_NAND_MODE_CTRL
#define C_NAND_WENLOW_1CYCLE      0x00000000    // P_NAND_MODE_CTRL
#define C_NAND_WENLOW_2CYCLE      0x00000100    // P_NAND_MODE_CTRL
#define C_NAND_WENLOW_3CYCLE      0x00000200    // P_NAND_MODE_CTRL
#define C_NAND_WENLOW_4CYCLE      0x00000300    // P_NAND_MODE_CTRL
#define C_NAND_WENHIGH_1CYCLE     0x00000000    // P_NAND_MODE_CTRL
#define C_NAND_WENHIGH_2CYCLE     0x00000400    // P_NAND_MODE_CTRL
#define C_NAND_WENHIGH_3CYCLE     0x00000800    // P_NAND_MODE_CTRL
#define C_NAND_WENHIGH_4CYCLE     0x00000C00    // P_NAND_MODE_CTRL
#define C_NAND_RENLOW_1CYCLE      0x00000000    // P_NAND_MODE_CTRL
#define C_NAND_RENLOW_2CYCLE      0x00001000    // P_NAND_MODE_CTRL
#define C_NAND_RENLOW_3CYCLE      0x00002000    // P_NAND_MODE_CTRL
#define C_NAND_RENLOW_4CYCLE      0x00003000    // P_NAND_MODE_CTRL
#define C_NAND_RENHIGH_1CYCLE     0x00000000    // P_NAND_MODE_CTRL
#define C_NAND_RENHIGH_2CYCLE     0x00004000    // P_NAND_MODE_CTRL
#define C_NAND_RENHIGH_3CYCLE     0x00008000    // P_NAND_MODE_CTRL
#define C_NAND_RENHIGH_4CYCLE     0x0000C000    // P_NAND_MODE_CTRL

#define C_NAND_TXBUF_EMPTY        0x00000001    // P_NAND_INT_CTRL, P_NAND_INT_STATUS