bios.c

44b0开发板试验代码ucos实验MP3.rar

/***********************************************
copyright by Haia Tech
www.haia2004.com
************************************************/

#include "..\inc\board.h"
#include "..\inc\bios.h"  
#include "..\inc\console.h"
#include "..\inc\flash.h" 


int counter=0; 
unsigned short pcm[200];

void sys_init(void)
{

	init_port(); 

//	outl(0x0e, rSYSCFG);    //enable cache 8K cache
	
//	outl(0x15569, rPCONE);
//	outl(0x06, rPUPE);
//	outl(0x10e, rPDATE); 
	
//	outl(0x1112,rBWSCON);  //16bit
//	outl(0x0f00,rBANKCON2);  //nGS2 8019 SRAM
//IIS SET	
//	outl(0x003d,rIISCON);   //DMA ENABLE
//	outl(0x01dd,rIISMOD);   //SLAVE MODE 16bit 384fs 32fs left-justied
//	outl(0x0,   rIISPSR);   //
//	outl(0x0f00,rIISFCON);  //

//IIS SET	
	outl(0x0033,rIISCON);   //DMA ENABLE
	outl(0x009d,rIISMOD);   //MSATER MODE 16bit 384fs 32fs left-justied
	outl(0x11,   rIISPSR);  //44.1k
	outl(0x0f00,rIISFCON);  //
	
//DMA SET	
	outl(0x0,rBDCON0);     //ENABLE DMA0  send
	outl((unsigned)pcm|(5<<28),rBDISRC0); //address for sourse half word
	outl(IISFIF|(7<<28),rBDIDES0); //sourse of address  half word
	outl(16|(0x44e<<20),rBDICNT0); //count=16,(habit DMA) IIS  interupt  
    delay(10);
	outl(16|(0x44f<<20),rBDICNT0); //count=16,EN DMA IIS  interupt
	
	
	init_Isr(); 
	init_timer(); 
} 
unsigned char *bios_main(void)
{
	unsigned char *exec_addr;
	unsigned short *buf;
	unsigned long startup_mode;
	int i, ch;

    for(i=0;i<200;i++)
      pcm[i]=0xf0f0;

	sys_init();
	
	init_AIC23();
	
	beep(1);
	

	delay(50000);
	beep(0);
	
   
	mp3();
	
    while(1);

}



void init_port(void)
{ 
	//CAUTION:Follow the configuration order for setting the ports. 
	// 1) setting value 
	 // 2) setting control register 
	 // 3) configure pull-up resistor.  

	//16bit data bus configuration  
  
	// PORT A GROUP
	/*  BIT 9		8	7	6	5	4	3	2	1	0	*/
	/*        A24	A23	A22	A21	A20	A19	A18	A17	A16	A0	*/	      
	/*        1		1	1	1	1	1	1	1	1	1	*/
	outl(0x1ff,rPCONA);	

	// PORT B GROUP
	/*  BIT 10	9		8		7		6		5		4		3		2		1		0		*/
	/*	/CS5	/CS4	/CS3	/CS2	/CS1	nWBE3	nWBE2	/SRAS	/SCAS	SCLK	SCKE	*/
	
	/*	EXT		NIC		USB		IDE		SMC		NC		NC		Sdram	Sdram	Sdram	Sdram	*/
	/*      1,        1,   1,   1,    1,    1,       1,     1,    1,    1,   1          */
	outl(0x3ff,rPDATB);
	outl(0x3ff,rPCONB);
    
	//PORT C GROUP
	//BUSWIDTH=16													*/
	/*  PC15		14		13		12		11		10		9		8	*/
	/*	I		I		RXD1	TXD1	I		I		I		I	*/
	/*	NC		NC		Uart1	Uart1	NC		NC		NC		NC	*/
	/*   00		00		11		11		00		00		00		00	*/

	/*  PC7		6		5		4		3		2		1		0	*/
	/*   I		I		I		I		I		I		I		I	*/
	/*   NC		NC		NC		NC		SMCALE	SMCCLE	SMCCE	SMCRB*/
	/*   00		00		00		00		01		01		01		00	*/
	outl(0xffff,rPDATC);		//All IO is high
	outl(0x0f000054,rPCONC);	
	outl(0x3000,rPUPC);			//PULL UP RESISTOR should be enabled to I/O

	//PORT D GROUP
	/*  PORT D GROUP(I/O OR LCD)										*/
	/*  BIT7		6		5		4		3		2		1		0	*/
	/*      VF		VM		VLINE	VCLK	VD3		VD2		VD1		VD0	*/
	/*	   00		00		00		00		00		00		00		00	*/
	outl(0xff,rPDATD);
	outl(0x0,rPCOND);	
	outl(0x0,rPUPD);
	//These pins must be set only after CPU's internal LCD controller is enable
	
	//PORT E GROUP 
	/*  Bit 8		7		6		5		4		3		2		1		0		*/
	/*      CODECLK	LED4	LED5	LED6	LED7	BEEP	RXD0	TXD0	LcdDisp	*/ 
	/*      10		01		01		01		01		01		10		10		01		*/
	outl(0x1ff,rPDATE);
//	outl(0x25569,rPCONE);	
	outl(0x15569,rPCONE);	//NO CODECLK
	outl(0x6,rPUPE);
	
	//PORT F GROUP
	/*  Bit8		7		6		5		 4		3		2		1		0		*/   
	/*  Input	Input	Input	Input	Input	   OUT	  Wait	  SDA      SCK   	*/
	/*	000		000		000		000		00		   01		10	   01		01		*/
	outl(0xff,rPDATF);
	outl(0x000065,rPCONF);
	outl(0x0,rPUPF);

	//PORT G GROUP
	/*  BIT7		6		5		4		 3		2		1		0	 */
	/*	INT7		INT6  INT5  	INT4	INT3  INT2	  INT1   INT0	*/
	/*  IISLRCK	   IIDSO  IISDI     ISCLK	LED0  RST8019	IDE	 INT */
	/*      10      10      10      10      01      01      11      11       */
	outl(0xff,rPDATG);
	outl(0xaa5f,rPCONG);
	outl(0x0,rPUPG);	//should be enabled  
	
		
	outl(0xf7,rPDATG);    //LED is ON
	
	delay(1000);
	outl(0xf3,rPDATG);    //RST8019 0;
	
	outl(0x7,rSPUCR);  //D15-D0 pull-up disable

	/*定义非Cache区*/
	//outl(((Non_Cache_End>>12)<<16)|(Non_Cache_Start>>12),rNCACHBE0);
	
	
	/*所有的外部硬件中断为低电平触发*/
	outl(0x0,rEXTINT);
}



int init_timer()
{
	outl(0x00212121, rTCFG0);		//66MHz/33=2MHz
	outl(0x00000000, rTCFG1);		//every timer input is 1MHz
	outl(100000000, rTCNTB0);		//interrupt for every 100ms
	outl(0x0000000a, rTCON);		//set timer0 in auto reload mode
	outl(0x00000009, rTCON);		//start timer0
	return 0;
}
	
int init_Isr()
{
	outl(0x00000001, rINTCON);		//enable IRQ,disable FIQ
	outl(0x00000000, rINTMOD);		//all use IRQ mode
	outl(~(BIT_TIMER0 | BIT_GLOBAL|BIT_BDMA0|BIT_BDMA1), rINTMSK);		//enable timer0 interrupt
	
	hook(timer0_isr, pISR_TIMER0);	//pISR_TIMER0 is initialized to timer0_isr
	hook(BDMA0_isr, pISR_BDMA0);	//pISR_TIMER0 is initialized to timer0_isr
	hook(BDMA1_isr, pISR_BDMA1);	//pISR_TIMER0 is initialized to timer0_isr
	return 0;
}
 
void beep(int BeepStatus)
{
	if (BeepStatus==0)
		outl(inl(rPDATE)|0x08,rPDATE);
	else
		outl(inl(rPDATE)&0x1f7,rPDATE);

}


void __irq timer0_isr(void)
{
    int i;
	outl(BIT_TIMER0, rI_ISPC);		//clear interrupt pending bit
//	counter++;

	if(counter)
	{
 	    counter=0;
 	    for(i=0;i<16;i++)
  	      pcm[i]=0x7fff; 
	} 
	else
	{
	  counter=1;
 	    for(i=0;i<16;i++)
  	      pcm[i]=0x00; 
	}
	
}
void __irq BDMA0_isr(void)
{
	outl(BIT_BDMA0, rI_ISPC);		//clear interrupt pending bit
}
void __irq BDMA1_isr(void)
{
	outl(BIT_BDMA1, rI_ISPC);		//clear interrupt pending bit
}


void delay(int i)
{
    for(i;i>0;i--);
}