📄 pcrreg.v
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`include "div1.v"
module PcrReg( ResetN, CLKM,
PCRn, NxtPCRn, // pcrctrl
SPCR0, SPCR1, SPCR2, SetFNum, IData, SetPCREn, // csm
PCR12, FNUM, TF,DivEn, TF_En,// divider
PCRnV, RdEndIn , RdEndOut,
TF2_EN, PCR_ERR,
//debug
TF2
);
input ResetN;
input CLKM;
input [15:0] IData;
input SPCR0;
input SPCR1;
input SPCR2;
input SetFNum;
input [32:0] TF;
input TF_En;
input NxtPCRn;
input RdEndIn;
output SetPCREn;
output [32:0] PCRn;
output [32:0] PCR12;
output [11:0] FNUM;
output DivEn;
output PCRnV;
output RdEndOut;
output TF2_EN;
output PCR_ERR;
//debug
output [32:0] TF2;
//debug
reg SetPCREn;
reg DivEn;
reg [32:0] PCR1;
reg [32:0] PCR2;
reg [32:0] PCR3;
reg [11:0] FNUM1;
reg [11:0] FNUM2;
reg [11:0] FN;
reg pcr1v;
reg pcr2v;
reg [2:0] cur_st;
reg PCRnV;
reg RdEndOut;
reg pcr2v_reg;
reg SetPCREn_reg;
reg NxtPCRn_reg;
reg TF2_EN_reg;
wire pcr2v_ng;
wire SetPCREn_ng;
wire NxtPCRn_pg;
wire TF2_EN_pg;
wire pcr2v_en;
parameter INIT1 = 3'b000, INIT2 = 3'b001, EnPCRDiv = 3'b011,
WaitNxtFm = 3'b111, GetNxtFmPCR = 3'b110, GetNxtSegPCR = 3'b101;
assign PCRn = PCR1;
assign FNUM = FNUM1;
assign PCR12 = PCR2 - PCR1;
assign pcr2v_ng = ~pcr2v & pcr2v_reg;
assign SetPCREn_ng = ~SetPCREn & SetPCREn_reg;
assign NxtPCRn_pg = NxtPCRn & ~NxtPCRn_reg;
assign TF2_EN_pg = TF2_EN & ~TF2_EN_reg;
assign pcr2v_en = TF2_EN_pg & ~PCR_ERR;
//debug
wire [32:0] PCR23;
reg DivEn2;
wire [32:0] TF2;
assign PCR23 = PCR3 - PCR2;
assign PCR_ERR = TF2_EN && (( TF2<33'd33 ) || ( TF2>33'd677 ));
div1 U1( .ResetN(ResetN),
.CLKM(CLKM),
.dividend(PCR23),
.divisor(FNUM2),
.quotient(TF2),
.DivEn(DivEn2),
.Quo_Valid(TF2_EN)
);
//debug
always @(posedge CLKM)
begin
SetPCREn_reg <= SetPCREn;
pcr2v_reg <= pcr2v;
NxtPCRn_reg <= NxtPCRn;
TF2_EN_reg <= TF2_EN;
end
always @(posedge CLKM or negedge ResetN)
begin
if(!ResetN) begin
PCR1 <= 0;
PCR2 <= 0;
FNUM1 <= 0;
FN <= 0;
pcr1v <= 0;
pcr2v <= 0;
DivEn <= 0;
PCRnV <= 0;
cur_st <= 0;
RdEndOut <= 0;
end
else begin
case (cur_st)
INIT1 : begin
PCR1 <= 0;
PCR2 <= 0;
FNUM1 <= 0;
FN <= 0;
pcr1v <= 0;
pcr2v <= 0;
DivEn <= 0;
PCRnV <= 0;
cur_st <= INIT2;
RdEndOut <= 0;
end
INIT2 : begin
if(SPCR0) begin
PCR1[32:17] <= IData;
PCR2[32:17] <= IData;
end else if(SPCR1) begin
PCR1[16:1] <= IData;
PCR2[16:1] <= IData;
end else if(SPCR2) begin
PCR1[0] <= IData[15];
PCR2[0] <= IData[15];
end else if(SetFNum) begin
FNUM1 <= IData[11:0] - 1;
if(IData[11:0] == 1)
cur_st <= GetNxtSegPCR;
else
cur_st <= EnPCRDiv;
end
pcr1v <= 0;
pcr2v <= 0;
DivEn <= 0;
FN <= 0;
PCRnV <= 0;
RdEndOut <= 0;
end
EnPCRDiv : begin
cur_st <= WaitNxtFm;
PCR1 <= PCR1;
PCR2 <= PCR2;
pcr1v <= 1;
pcr2v <= 0;
DivEn <= 1;
FN <= 0;
PCRnV <= 1;
RdEndOut <= 0;
end
WaitNxtFm : begin
if(NxtPCRn_pg) begin
FN <= FN + 1;
if(FN==(FNUM-1))
cur_st <= GetNxtSegPCR;
else
cur_st <= GetNxtFmPCR;
end
PCR1 <= PCR1;
PCR2 <= PCR2;
pcr1v <= 1;
// if(SetPCREn_ng)
if(pcr2v_en)
pcr2v <= 1;
else
pcr2v <= pcr2v;
PCRnV <= 1;
DivEn <= 0;
RdEndOut <= 0;
end
GetNxtFmPCR : begin
if(TF_En) begin
PCR1 <= PCR1 + TF;
cur_st <= WaitNxtFm;
end
else begin
PCR1 <= PCR1;
cur_st <= cur_st;
end
PCR2 <= PCR2;
pcr1v <= 1;
// if(SetPCREn_ng)
if(pcr2v_en)
pcr2v <= 1;
else
pcr2v <= pcr2v;
DivEn <= 0;
RdEndOut <= 0;
end
GetNxtSegPCR : begin
PCRnV <= 0;
if(pcr2v==1) begin
cur_st <= EnPCRDiv;
PCR1 <= PCR2;
PCR2 <= PCR3;
FNUM1 <= FNUM2;
pcr1v <= 1;
pcr2v <= 0;
FN <= 0;
DivEn <= 0;
RdEndOut <= 0;
end
else begin
cur_st <= GetNxtSegPCR;
PCR1 <= PCR1;
PCR2 <= PCR2;
// if(SetPCREn_ng)
if(pcr2v_en)
pcr2v <= 1;
else
pcr2v <= pcr2v;
FNUM1 <= FNUM1;
pcr1v <= 1;
FN <= 0;
DivEn <= 0;
RdEndOut <= RdEndIn;
end
end
endcase
end
end
always @(posedge CLKM or negedge ResetN)
begin
if(!ResetN) begin
PCR3 <=0;
FNUM2 <= 0;
SetPCREn <= 0;
DivEn2 <= 0; //debug
end
else begin
if(pcr1v==0)
SetPCREn <= 1;
else if(pcr2v_ng)
SetPCREn <= 1;
else if(SetFNum)
SetPCREn <= 0;
else
SetPCREn <= SetPCREn;
if(pcr1v) begin
if(SPCR0) begin
PCR3[32:17] <= IData;
DivEn2 <= 0; // debug
end
else if(SPCR1)
PCR3[16:1] <= IData;
else if(SPCR2)
PCR3[0] <= IData[15];
else if(SetFNum) begin
FNUM2 <= IData[11:0];
DivEn2 <= 1; // debug
end
end
else begin
PCR3 <= PCR3 ;
FNUM2 <= FNUM2;
// DivEn2 <= DivEn2; // debug
DivEn2 <= 0;
end
end
end
endmodule
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