getpcrsegaddr.v

华大机顶盒源码(包括所有源代码).rar

module GetPCRSegAddr( CLKM, ResetN,
                      //input 
                      PCRSeg, FindPCRSegA_En, RegBusy, 
                      RT_DB, CompNewSeg_End, 
                      //output
                      RdPCR_En, SegAddr, FindPCRSegA_End,
                      rdpcr_oper, RT_RD, RT_ADDR
                      //debug
                    );

input        CLKM;  
input        ResetN;

input  [11:0]  PCRSeg;
input         FindPCRSegA_En;
input         RegBusy;
input  [7:0]  RT_DB;
input         CompNewSeg_End;

output        RdPCR_En;
output [27:0] SegAddr;
output        FindPCRSegA_End;
output        rdpcr_oper;
output        RT_RD;
output [9:0]  RT_ADDR;

reg           RdPCR_En;
reg    [27:0] SegAddr;
reg           FindPCRSegA_End;
reg           rdpcr_oper;
reg           RT_RD;
reg    [9:0]  RT_ADDR;

reg    [5:0]  CurState;

parameter Idle  = 5'd0 ,     RdSegNum1 = 5'd1  , RdSegNum2 = 5'd2  , RdSegNum3 = 5'd3 ,
          RdSegNum4 = 5'd4 , RdSA1     = 5'd5  , RdSA2     = 5'd6  , RdSA3 = 5'd7 ,
          RdSA4 = 5'd8 ,     RdPCRSAEn = 5'd9  , RdEA1     = 5'd10 , RdEA2 = 5'd11,
          RdEA3 = 5'd12,     RdEA4     = 5'd13 , RdEA5     = 5'd14 , RdEA6 = 5'd15,
          RdEA7 = 5'd16,     RdEA8     = 5'd17 , OperEnd   = 5'd18 , WaitNewSeg = 5'd19;
          
always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	RdPCR_En <= 0;
	SegAddr <= 0;
	FindPCRSegA_End <= 0;
	rdpcr_oper <= 0;
	RT_RD <= 0;
	RT_ADDR <= 0;
	CurState <= Idle;
end
else begin
	case (CurState)
		Idle : 
		begin
			if(!FindPCRSegA_En)
				FindPCRSegA_End <= 0;
			RT_RD <= 0;
			RT_ADDR <= 0;
			if(FindPCRSegA_En && !RegBusy && !FindPCRSegA_End) begin
				rdpcr_oper <= 1;
				CurState <= RdSegNum1;
				RdPCR_En <= 0;
			end
			else begin
				rdpcr_oper <= 0;
				CurState <= Idle;
				RdPCR_En <= RdPCR_En;
			end
		end
		RdSegNum1 :
		begin
			RT_RD <= 1;
			CurState <= RdSegNum2;	
		end
		RdSegNum2 :
		begin
			RT_RD <= 0;
	                if(RT_DB==8'hFF) begin
	                	rdpcr_oper <= 0;
	                	CurState <= WaitNewSeg;
	                end
	                else if(RT_DB==PCRSeg[11:4]) begin
	         		RT_ADDR[2:0] <= 3'b001;
	         		CurState <= RdSegNum3;
	         	end
	         	else begin
	         		RT_ADDR[9:3] <= RT_ADDR[9:3] + 1;
	         		RT_ADDR[2:0] <= 3'b000;
	        		CurState <= RdSegNum1;
	        	end 		       		
		end
		RdSegNum3 :
		begin
			RT_RD <= 1;
			CurState <= RdSegNum4;
		end
		RdSegNum4 :
		begin
			RT_RD <= 0;
			if(RT_DB[7:4]==PCRSeg[3:0]) begin
				RdPCR_En <= 1;
				RT_ADDR[2:0] <= 3'b010;
				CurState <= RdSA1;
			end
			else begin
				RT_ADDR[9:3] <= RT_ADDR[9:3] + 1;
				RT_ADDR[2:0] <= 3'b000;
				CurState <=RdSegNum1;
			end
		end	         	
			
		RdSA1 : 
		begin
			RT_RD <= 1;
			CurState <= RdSA2;
		end
		RdSA2 :
		begin
			RT_RD <= 0;
			SegAddr[11:0] <= 0;
			SegAddr[19:12] <= RT_DB;
			RT_ADDR[2:0] <= 3'b011;
			CurState <= RdSA3;
		end
		RdSA3 :
		begin
			RT_RD <= 1;
			CurState <= RdSA4;
		end
		RdSA4 :
		begin
			RT_RD <= 0;
			SegAddr[27:20] <= RT_DB;
			RT_ADDR[2:0] <= 3'b100;
			CurState <= RdPCRSAEn;
		end		
		RdPCRSAEn :
		begin
			FindPCRSegA_End <= 1;
			if(!FindPCRSegA_En) 
				CurState <= RdEA1;
		end
		RdEA1 :
		begin
			RT_RD <= 1;
			CurState <= RdEA2;
		end
		RdEA2 :
		begin
			RT_RD <= 0;
			SegAddr[7:0] <= RT_DB;
			RT_ADDR[2:0] <= 3'b101;
			CurState <= RdEA3;
		end
		RdEA3 :
		begin
			RT_RD <= 1;
			CurState <= RdEA4;
		end
		RdEA4 :
		begin
			RT_RD <= 0;
			SegAddr[15:8] <= RT_DB;
			RT_ADDR[2:0] <= 3'b110;
			CurState <= RdEA5;
		end
		RdEA5 :
		begin
			RT_RD <= 1;
			CurState <= RdEA6;
		end
		RdEA6 :
		begin
			RT_RD <= 0;
			SegAddr[23:16] <= RT_DB;
			RT_ADDR[2:0] <= 3'b111;
			CurState <= RdEA7;
		end
		RdEA7 :
		begin
			RT_RD <= 1;
			CurState <= RdEA8;
		end
		RdEA8 :
		begin
			RT_RD <= 0;
			SegAddr[27:24] <= RT_DB[4:0];
			RT_ADDR[2:0] <= 3'b000;
			CurState <= OperEnd;
		end
		OperEnd :
		begin
			FindPCRSegA_End <= 0;
			rdpcr_oper <= 0;
			CurState <= Idle;	
		end
		WaitNewSeg :
		begin
			FindPCRSegA_End <= 0;
			RT_RD <= 0;
			RT_ADDR <= 0;
			rdpcr_oper <= 0;
			if(CompNewSeg_End)
				CurState <= Idle;
		end
		default :
		begin
			CurState <= Idle;
		end
	endcase
end

endmodule