saveframebuf.v

华大机顶盒源码(包括所有源代码).rar

module SaveFrameBuf( CLKM, ResetN,
                     //input 
                     bInfo, bProg, FValid, FSync, Den, bDZTS,
                     BufEmpty, Rx_DB, CompDZTS_End,
                     //output
                     Rx_SelLW, CompDZTS_En,
                     FB_DB, FB_WR, FB_WAddr, FB_WEN,
                     SaveBufFull
                   );

input        CLKM;
input        ResetN;

input        bInfo;
input        bProg;
input        FValid;
input        FSync;
input        Den;
input        bDZTS;
input        BufEmpty;
input [15:0] Rx_DB;
input        CompDZTS_End;

output        Rx_SelLW;
output [15:0] FB_DB;
output        FB_WR;
output [6:0]  FB_WAddr;
output        FB_WEN;
output        SaveBufFull;
output        CompDZTS_En;

reg           Rx_SelLW;
reg           FB_WR;
reg [6:0]     FB_WAddr;
reg           SaveBufFull;
reg           CompDZTS_En;

wire SaveEn;
wire SaveEnd;

assign SaveEn = (!bInfo) && (!bProg) && FValid && FSync && Den && BufEmpty;
assign SaveEnd = bDZTS;
assign FB_DB = Rx_DB;
assign FB_WEN = 1'b1;

reg [5:0] CurState;

parameter BufLen = 7'h5E;
parameter Idle = 6'b000001,
          WrHW1 = 6'b000010,
          WrHW2 = 6'b000100,
          WrLW1 = 6'b001000,
          WrLW2 = 6'b010000,
          WaitNxtData = 6'b100000;

always @(posedge CLKM or negedge ResetN)
if(!ResetN)
	CompDZTS_En <= 0;
else if(FSync && Den && !bInfo && !bProg)
	CompDZTS_En <= 1;
else if(CompDZTS_End)
	CompDZTS_En <= 0;

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	Rx_SelLW <= 0;
	FB_WR <= 0;
        FB_WAddr <= 0;
        SaveBufFull <= 0;	
	CurState <= Idle;
end
else begin
	case (CurState)
		Idle : 
		begin
			Rx_SelLW <= 0;
			FB_WR <= 0;
		        FB_WAddr <= 0;
		        SaveBufFull <= 0;	
			if(SaveEn)
				CurState <= WrHW1;
		end
		WrHW1 :
		begin
			FB_WR <= 1;
			CurState <= WrHW2;	
		end
		WrHW2 :
		begin
			FB_WR <= 0;
			Rx_SelLW <= 1;
			FB_WAddr <= FB_WAddr + 1;
			CurState <= WrLW1;
		end
		WrLW1 :
		begin
			FB_WR <= 1;
			CurState <= WrLW2;
		end
		WrLW2 :
		begin
			FB_WR <= 0;
			Rx_SelLW <= 0;
			FB_WAddr <= FB_WAddr + 1;
			CurState <= WaitNxtData;
		end
		WaitNxtData :
		begin
			if(SaveEnd) begin
				CurState <= Idle;
			end
			else if(FB_WAddr==BufLen) begin
			        SaveBufFull <= 1;	
				CurState <= Idle;	
			end
			else if(Den) begin
				CurState <= WrHW1;
			end
			else begin
				CurState <= WaitNxtData;
			end
		end
		default :
		begin
			CurState <= Idle;
		end
	endcase
end

endmodule