dvbuf.v

来自「华大机顶盒源码(包括所有源代码).rar」· Verilog 代码 · 共 68 行

module dvbuf(ResetN, CLKM, VALIDI, DVO
            //debug
            //dv1, st
            );

input ResetN;
input CLKM;
input VALIDI;
output DVO;
//output dv1;
//output [1:0] st;

reg dv1, dv2; 
reg st;

assign DVO = dv2;

/*always @(posedge CLKM or posedge VALIDI or negedge ResetN) 
if(!ResetN)
   dv1 <= 0;
else if(VALIDI)
   dv1 <= 1;
else 
   dv1 <= 0;
*/
always @(posedge CLKM or posedge VALIDI or negedge ResetN) 
if(!ResetN)
   dv1 <= 0;
else if(VALIDI)
   dv1 <= 1;
else 
   dv1 <= 0;
/*
always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
   st <= 0;
   dv2 <= 0;
end
else begin
   case (st)
     1'b0 : begin
             if(dv1) begin
                st <= 1;
                dv2 <= 1;
             end
             else begin
                st <= 0;
                dv2 <= 0;
             end
             end
     1'b1 : begin
             st <= 0;
             dv2 <= 0;
             end
   endcase
end
*/

always @(posedge CLKM or negedge ResetN)
if(!ResetN)
   dv2 <= 0;
else if(!dv2)
   dv2 <= dv1;
else
   dv2 <= 0;
   
endmodule