txframebuf.v

来自「华大机顶盒源码(包括所有源代码).rar」· Verilog 代码 · 共 110 行

module TxFrameBuf( CLKM , ResetN,
                   //input 
                   EPGDataReq, FB_RDB, 
                   //output 
                   EPGData,  EPGWrEn,  EPGAddr,
                   FB_RD, FB_RAddr,
                   EPGTxEnd 
                 );
                 
input         CLKM;
input         ResetN;

input         EPGDataReq;
input [15:0]  FB_RDB;               

output [15:0] EPGData;
output        EPGWrEn;
output        EPGAddr;
output        FB_RD;
output [6:0]  FB_RAddr;
output        EPGTxEnd;

reg           EPGWrEn;
reg           EPGAddr;
reg           FB_RD;
reg    [6:0]  FB_RAddr;
reg           EPGTxEnd;

assign EPGData = FB_RDB;

reg [5:0] CurState;

parameter BufLen = 7'h5E;
parameter Idle = 6'b000001,
          RdHW1 = 6'b000010,
          RdHW2 = 6'b000100,
          RdLW1 = 6'b001000,
          RdLW2 = 6'b010000,
          WaitNxtReq = 6'b100000;


always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	EPGWrEn <= 0;
	EPGAddr <= 0;
	FB_RD <= 0;
	FB_RAddr <= 0;
	EPGTxEnd <= 0;
	CurState <= Idle;
end
else begin
	case (CurState)
		Idle : 
		begin
			EPGWrEn <= 0;
			EPGAddr <= 0;
			FB_RD <= 0;
			FB_RAddr <= 0;
			EPGTxEnd <= 0;
			if(EPGDataReq)
				CurState <= RdHW1;
		end
		RdHW1 :
		begin
			EPGWrEn <= 1;
			FB_RD <= 1;
			CurState <= RdHW2;			
		end
		RdHW2 :
		begin
			EPGWrEn <= 0;
			FB_RD <= 0;
			FB_RAddr <= FB_RAddr + 1;
			CurState <= RdLW1;
		end
		RdLW1 :
		begin
			EPGWrEn <= 1;
			EPGAddr <= 1;
			FB_RD <= 1;
			CurState <= RdLW2;
		end
		RdLW2 :
		begin
			EPGWrEn <= 0;
			EPGAddr <= 0;
			FB_RD <= 0;
			FB_RAddr <= FB_RAddr + 1;
			CurState <= WaitNxtReq;
		end
		WaitNxtReq :
		begin
			if(FB_RAddr==BufLen) begin
				EPGTxEnd <= 1;
				CurState <= Idle;
			end
			else if(EPGDataReq)
				CurState <= RdHW1;
			else 
				CurState <= WaitNxtReq;
		end
		default :
			CurState <= Idle;
	endcase 
end



endmodule