txaddrreg.v

华大机顶盒源码(包括所有源代码).rar

module TxAddrReg( CLKM, ResetN,
                  //input 
                  IncEn, RdPCR_En, SegAddr, FindTxSegA_End, 
                  Max_Seg_Num,
                  //
                  FindTxSegA_En, TxAddr, Tx_En, TxSeg, ProgEnd
                );

input        CLKM;
input        ResetN;

input        IncEn;
input        RdPCR_En;
input [27:0] SegAddr;
input        FindTxSegA_End;
input [11:0]  Max_Seg_Num;

output        FindTxSegA_En;
output [27:0] TxAddr;
output        Tx_En;
output [11:0]  TxSeg;
output        ProgEnd;

reg           FindTxSegA_En;
reg    [25:0] sd_ra;
reg           Tx_En;
reg    [11:0]  TxSeg;
reg           ProgEnd;

assign TxAddr[1:0] = 2'b00;
assign TxAddr[27:2] = sd_ra;

reg [5:0] CurState;
parameter Idle = 3'b000,
          GetTxSegSA = 3'b001,
          ReadSA = 3'b011,
          IncRdAddr = 3'b010,
          NxtSeg = 3'b100;
          
always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	FindTxSegA_En <= 0;
	sd_ra <= 0;
	Tx_En <= 0;
	TxSeg <= 0;
	ProgEnd <= 0;
	CurState <= Idle;
end
else begin
	case (CurState)
		Idle : 
		begin
			FindTxSegA_En <= 0;
			sd_ra <= 0;
			Tx_En <= 0;
			TxSeg <= 0;
			ProgEnd <= 0;
			if(RdPCR_En)
				CurState <= GetTxSegSA;
		end
		GetTxSegSA :
		begin
			FindTxSegA_En <= 1;
			if(FindTxSegA_End)
				CurState <= ReadSA;
		end
		ReadSA :
		begin
			sd_ra <= SegAddr[27:2];			
			Tx_En <= 1;
			FindTxSegA_En <= 0;				
			CurState <= IncRdAddr;
		end
		IncRdAddr :
		begin
			if((sd_ra>= SegAddr[27:2]) && !FindTxSegA_End) begin
				TxSeg <= TxSeg+1;
				Tx_En <= 0;
				CurState <= NxtSeg;
			end
			else if(IncEn) begin
				sd_ra <= sd_ra + 1;
			end
		end
		NxtSeg :
		begin
			if(TxSeg >= Max_Seg_Num) begin
				ProgEnd <= 1;
				CurState <= Idle;
			end
			else begin
				CurState <= GetTxSegSA;
			end
		end
		default :
		begin
			CurState <= Idle;
		end
	endcase
end

endmodule