pcraddrreg.v

华大机顶盒源码(包括所有源代码).rar

module PCRAddrReg( CLKM, ResetN,
                   //input 
                   IncEn, NxtFrame, SegAddr, Init_Mem_End, FindPCRSegA_End, Max_Seg_Num, 
                   //output 
                   PCRSeg, FindPCRSegA_En, RdPCREnd, PcrAddr, PCR_En);

input         CLKM;
input         ResetN;

input         IncEn;
input         NxtFrame;
input [27:0]  SegAddr;
input         FindPCRSegA_End;
input         Init_Mem_End;
input [11:0]   Max_Seg_Num;

output [11:0]  PCRSeg;
output        FindPCRSegA_En;
output        RdPCREnd;
output [27:0] PcrAddr;
output        PCR_En;

reg    [11:0]  PCRSeg;
reg           FindPCRSegA_En;
reg    [25:0] pcr_ra;
reg    [2:0]  CurState;
reg           PCR_En;
reg    [5:0]  PCRCNT;

assign RdPCREnd = (PCRSeg>=Max_Seg_Num);
assign PcrAddr[1:0] = 2'b00;
assign PcrAddr[27:2] = pcr_ra;

parameter Idle = 3'd0, GetPCRSA = 3'd1, ReadPCRSA = 3'd2,
          IncPCRAddr = 3'd3,  NxtSeg = 3'd4;

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	PCRSeg <= 0;
	FindPCRSegA_En <= 0;
	pcr_ra <= 0;
	PCR_En <= 0;
	PCRCNT <= 0;
	CurState <= 0;
end
else begin
	case (CurState)
		Idle :
		begin
			PCRSeg <= 0;
			FindPCRSegA_En <= 0;
			pcr_ra <= 0;
			PCR_En <= 0;
			PCRCNT <= 0;
			if(Init_Mem_End)
				CurState <= GetPCRSA;
		end
		GetPCRSA : 
		begin
			FindPCRSegA_En <= 1;
			if(FindPCRSegA_End)
				CurState <= ReadPCRSA;
		end
		ReadPCRSA :
		begin
			pcr_ra <= SegAddr[27:2];
			PCR_En <= 1;
			FindPCRSegA_En <= 0;
			PCRCNT <= 6'h2F;
			CurState <= IncPCRAddr;
		end
		IncPCRAddr :
		begin
			if((pcr_ra >= SegAddr[27:2]) && !FindPCRSegA_End) begin
				PCRSeg <= PCRSeg + 1;
				PCR_En <= 0;
				CurState <= NxtSeg;
			end
			else if(IncEn) begin
				pcr_ra <= pcr_ra + 1;
				PCRCNT <= PCRCNT - 1;
			end
			else if(NxtFrame) begin
				pcr_ra <= pcr_ra + PCRCNT;
				PCRCNT <= 6'h2F;
			end
		end
		NxtSeg :
		begin
			if(PCRSeg >= Max_Seg_Num) begin
				CurState <= NxtSeg;
			end
			else begin
				CurState <= GetPCRSA;
			end
		end
		default :
		begin
			CurState <= Idle;
		end
	endcase
end



endmodule