ctlfb.v

来自「华大机顶盒源码(包括所有源代码).rar」· Verilog 代码 · 共 44 行

module CtlFB( CLKM, ResetN, 
              //input 
              SaveBufFull, EPGTxEnd,
              //output
              BufEmpty, EPGTxEn, WRCS, RDCS
            );

input 	     CLKM;
input        ResetN;

input        SaveBufFull;
input        EPGTxEnd;

output       BufEmpty;
output       EPGTxEn;
output [2:0] WRCS;
output [2:0] RDCS;

reg    [7:0] BufFull;
reg    [2:0] WRCS;
reg    [2:0] RDCS;

assign BufEmpty = ~BufFull[WRCS];
assign EPGTxEn = BufFull[RDCS];

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	BufFull <= 0;
	WRCS <= 0;
	RDCS <= 0;
end 
else begin
	if(SaveBufFull) begin
		BufFull[WRCS] <= 1;
		WRCS <= WRCS + 1;
	end
	if(EPGTxEnd) begin
		BufFull[RDCS] <= 0;
		RDCS <= RDCS + 1;
	end
end

endmodule