📄 csm.v
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module csm( CLKM, ResetN,
//RxModule
RxData, RxFsync, RxDen, RxDaMux,
//CompPID
bProg,
//SaveSegReg
SaveEn,
//WrAddrReg
WrAddr, WrNewSeg, WrIncEn, WrNxtFr,
//TxAddrReg
TxAddr, TxIncEn, TxEn,
//PCRAddrReg
PCRAddr, PCRIncEn, PCRNxtFr, PCREn, RdPCREnd,
//Txmodule
TxData, Addr, WrEn, TxDataReq,
//PCRREG
SPCR0, SPCR1, SPCR2, SetFNUM, SetData, SetPCREn, RdEnd,
//PCRCTL
Send_0Frame, TxFSYNC,
//SDRAM controller
SRAM_DI, SRAM_DO, SRAM_WR, SRAM_RD, SRAM_FRESH, SRAM_AD,
SD_RD_ENA, SD_BURST_LEN, SD_DATA_ENA,
//System
TF2_EN, PCR_ERR
);
input CLKM;
input ResetN;
//RxModule
input [15:0] RxData;
input RxFsync;
input RxDen;
output RxDaMux;
//CompPID
input bProg;
//SaveSegReg
input SaveEn;
//WrAddrReg
input [27:0] WrAddr;
input WrNewSeg;
output WrIncEn;
output WrNxtFr;
//TxAddrReg
input [27:0] TxAddr;
input TxEn;
output TxIncEn;
//PCRAddrReg
input [27:0] PCRAddr;
input PCREn;
input RdPCREnd;
output PCRIncEn;
output PCRNxtFr;
//TxModule
input TxDataReq;
output [15:0] TxData;
output Addr;
output WrEn;
//PCRReg
input SetPCREn;
output SPCR0;
output SPCR1;
output SPCR2;
output SetFNUM;
output [15:0] SetData;
output RdEnd;
//PCRCtl
output Send_0Frame;
output TxFSYNC;
//SDRAM Controller
input [15:0] SRAM_DI;
input SD_RD_ENA;
input [3:0] SD_BURST_LEN;
input SD_DATA_ENA;
output [15:0] SRAM_DO;
output SRAM_WR;
output SRAM_RD;
output SRAM_FRESH;
output [27:0] SRAM_AD;
//system
input TF2_EN;
input PCR_ERR;
//
reg WrIncEn;
reg WrNxtFr;
reg TxIncEn;
reg PCRIncEn;
reg PCRNxtFr;
reg TxFSYNC;
reg Send_0Frame;
reg SPCR0;
reg SPCR1;
reg SPCR2;
reg SetFNUM;
reg [15:0] SetData;
reg SRAM_WR;
reg SRAM_RD;
reg SRAM_FRESH;
//internal register
reg sd_rd_en;
reg rdpcr_en;
reg [11:0] pcr_fnum;
reg [31:0] pcrbuf;
reg [5:0] TCNT;
reg WR_EN;
reg RD_EN;
reg set_first_pcr;
reg [2:0] pcr_st;
reg [5:0] cur_st;
reg [5:0] nxt_st;
parameter FRAME_CNT = 6'd47;
parameter IDLE = 6'd0, WRS0 = 6'd1, WRS01 = 6'd2, WRS1 = 6'd3,
WRS2 = 6'd4, WRS3 = 6'd5, WRS4 = 6'd6,
WRS5 = 6'd7, WRS6 = 6'd8, WRS7 = 6'd9,
WRS8 = 6'd10, RDS0 = 6'd11, RDS1 = 6'd12,
RDS2 = 6'd13, RDS3 = 6'd14, RDS4 = 6'd15,
RDS5 = 6'd16, RDS6 = 6'd17, RDS7 = 6'd18,
RDS8 = 6'd19, RDS9 = 6'd20,
WAIT_DEN = 6'd21,
REFRESH1 = 6'd22, REFRESH2 = 6'd23,
REFRESH3 = 6'd39, REFRESH4 = 6'd40,
PCRS0 = 6'd24, PCRS1 = 6'd25, PCRS2 = 6'd26,
PCRS3 = 6'd27, PCRS4 = 6'd28, PCRS5 = 6'd29,
PCRS6 = 6'd30, PCRS7 = 6'd31, PCRS8 = 6'd32,
PCRS9 = 6'd33, PCRS10 = 6'd34, PCRS11 = 6'd35,
SENDPEND0 = 6'd36, SENDPEND1=6'd37, SENDPEND2=6'd38;
assign RxDaMux = SD_DATA_ENA ? SD_BURST_LEN[0] : 0;
assign TxData = SRAM_DI;
assign WrEn = sd_rd_en ? SD_RD_ENA : 0;
assign Addr = sd_rd_en ? SD_BURST_LEN[0] : 0;
assign SRAM_DO = RxData;
assign SRAM_AD[18:0] = rdpcr_en ? PCRAddr[18:0] : (sd_rd_en ? TxAddr[18:0] : WrAddr[18:0]);
assign SRAM_AD[19] = (~SRAM_FRESH) || (rdpcr_en ? PCRAddr[19] : (sd_rd_en ? TxAddr[19] : WrAddr[19]));
assign SRAM_AD[27:20] = rdpcr_en ? PCRAddr[27:20] : (sd_rd_en ? TxAddr[27:20] : WrAddr[27:20]);
assign RdEnd = RdPCREnd;
always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
pcrbuf <= 0;
end
else if(SD_RD_ENA/* && rdpcr_en*/) begin
if(SD_BURST_LEN[0])
pcrbuf[15:0] <= SRAM_DI;
else
pcrbuf[31:16] <= SRAM_DI;
end
always @(posedge CLKM or negedge ResetN)
begin
if(!ResetN)
cur_st <= IDLE;
else
cur_st <= nxt_st;
end
always @(ResetN or cur_st or RxDen or RxFsync or TxDataReq or TxEn or
PCREn or SD_BURST_LEN or pcr_st )
begin
if(!ResetN) begin
nxt_st <= IDLE;
end
else begin
case (cur_st)
IDLE : begin
if(RxDen)
nxt_st <= WRS0;
else
nxt_st <= IDLE;
end
WRS0 : begin //if to write into sdram, Set token
nxt_st <= WRS1;
end
WRS1 : begin //write: set sram_wr = 0 , set blktable if need
nxt_st <= WRS2;
end
WRS2 : begin //sram_wr = 0
nxt_st <= WRS3;
end
WRS3 : begin //SET sram_wr = 1
nxt_st <= WRS4;
end
WRS4 : begin
nxt_st <= WRS5; // 1
end
WRS5 : begin // 1
if(TxDataReq && TxEn)
nxt_st <= RDS0;
else if(RxFsync)
nxt_st <= REFRESH1;
else if(PCREn)
nxt_st <= PCRS0;
else
nxt_st <= WAIT_DEN;
end
RDS0 : begin //if can read
nxt_st <= RDS1;
end
RDS1 : begin // sdram_rd = 0
nxt_st <= RDS2;
end
RDS2 : begin // 0
nxt_st <= RDS3;
end
RDS3 : begin // 1
nxt_st <= RDS4;
end
RDS4 : begin // 1
if(SD_BURST_LEN[0])
nxt_st <= WAIT_DEN;
else
nxt_st <= RDS4;
end
REFRESH1 : begin // sram_fresh = 1
nxt_st <= REFRESH2;
end
REFRESH2 : begin // sram_fresh = 0;
nxt_st <= REFRESH3;
end
REFRESH3 : begin // 0
nxt_st <= REFRESH4;
end
REFRESH4 : begin // sram_fresh = 1;
nxt_st <= WAIT_DEN;
end
PCRS0 : begin
if((pcr_st==3'b000) || (pcr_st==3'b111) || (pcr_st==3'b101))
nxt_st <= WAIT_DEN;
else if(pcr_st==3'b100)
nxt_st <= PCRS5;
else
nxt_st <= PCRS1;
end
PCRS1 : begin //sram_rd = 0
nxt_st <= PCRS2;
end
PCRS2 : begin // 0
nxt_st <= PCRS3;
end
PCRS3 : begin // 1
if(SD_BURST_LEN[0])
nxt_st <= PCRS4;
else
nxt_st <= PCRS3;
end
PCRS4 : begin // 1
// nxt_st <= WAIT_DEN;
if(RxDen)
nxt_st <= WRS0;
else
nxt_st <= WAIT_DEN;
end
PCRS5 : begin
nxt_st <= PCRS6;
end
PCRS6 : begin
nxt_st <= PCRS7;
end
PCRS7 : begin
nxt_st <= PCRS8;
end
PCRS8 : begin
// nxt_st <= WAIT_DEN;
if(RxDen)
nxt_st <= WRS0;
else
nxt_st <= WAIT_DEN;
end
WAIT_DEN : begin
if(RxDen)
nxt_st <= WRS0;
else
nxt_st <= WAIT_DEN;
end
default : begin
nxt_st <= IDLE;
end
endcase
end
end
always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
WrIncEn <= 0;
WrNxtFr <= 0;
TxIncEn <= 0;
PCRIncEn <= 0;
PCRNxtFr <= 0;
pcr_st <= 0;
TxFSYNC <= 1;
Send_0Frame <= 1;
SPCR0 <= 0;
SPCR1 <= 0;
SPCR2 <= 0;
SetFNUM <= 0;
SetData <= 0;
SRAM_WR <= 1;
SRAM_RD <= 1;
SRAM_FRESH <= 1;
sd_rd_en <= 0;
rdpcr_en <= 0;
pcr_fnum <= 0;
TCNT <= 0;
WR_EN <= 0;
RD_EN <= 0;
set_first_pcr <= 1;
end
else begin
case (cur_st)
IDLE :
begin
WrIncEn <= 0;
WrNxtFr <= 0;
TxIncEn <= 0;
PCRIncEn <= 0;
PCRNxtFr <= 0;
pcr_st <= 0;
TxFSYNC <= 1;
Send_0Frame <= 1;
SPCR0 <= 0;
SPCR1 <= 0;
SPCR2 <= 0;
SetFNUM <= 0;
SetData <= 0;
SRAM_WR <= 1;
SRAM_RD <= 1;
SRAM_FRESH <= 1;
sd_rd_en <= 0;
rdpcr_en <= 0;
pcr_fnum <= 0;
TCNT <= 0;
WR_EN <= 0;
RD_EN <= 0;
set_first_pcr <= 1;
end
WRS0 :
begin
WrIncEn <= 0;
TxIncEn <= 0;
PCRIncEn <= 0;
PCRNxtFr <= 0;
sd_rd_en <= 0;
rdpcr_en <= 0;
SPCR0 <= 0;
SPCR1 <= 0;
SPCR2 <= 0;
SetFNUM <= 0;
SRAM_WR <= 1'b1;
SRAM_RD <= 1'b1;
SRAM_FRESH <= 1'b1;
if(TCNT==6'd2 && Send_0Frame)
Send_0Frame <= 0;
if(RxFsync) begin // frame head
if(bProg && SaveEn) begin// can be writed to sdram
WR_EN <= 1;
if(!WrNewSeg)
WrNxtFr <= 1;
end
else begin // can't be writed
WR_EN <= 0;
end
end
end
WRS1 :
begin
WrNxtFr <= 0;
if(WR_EN)
SRAM_WR <= 1'b0;
else
SRAM_WR <= 1'b1;
end
WRS2 :
begin
SRAM_WR <= SRAM_WR;
end
WRS3 :
begin
SRAM_WR <= 1'b1;
end
WRS4 :
begin
if(WR_EN)
WrIncEn <= 1;
end
WRS5 :
begin
WrIncEn <= 0;
end
RDS0 :
begin
sd_rd_en <= 1;
end
RDS1 :
begin
SRAM_RD <= 1'b0;
end
RDS3 :
begin
SRAM_RD <= 1'b1;
end
RDS4 :
begin
if(SD_BURST_LEN[0]) begin
TxIncEn <= 1;
sd_rd_en <= 0;
if(TCNT==FRAME_CNT-1) begin
TCNT <= 0;
TxFSYNC <= 1'b1;
end
else begin
TCNT <= TCNT + 1;
TxFSYNC <= 1'b0;
end
end
end
REFRESH1 :
begin
SRAM_FRESH <= 1'b1;
end
REFRESH2 :
begin
SRAM_FRESH <= 1'b0;
end
REFRESH3 :
begin
SRAM_FRESH <= 1'b0;
end
REFRESH4 :
begin
SRAM_FRESH <= 1'b1;
end
PCRS0 :
begin
if(pcr_st==3'b000) begin
pcr_fnum <= 0;
// if((Send_0Frame && PCREn) || SetPCREn)
if(SetPCREn)
pcr_st <= 3'b001;
end
else if(pcr_st==3'b100) begin
SPCR1 <= 1;
pcr_fnum <= pcr_fnum + 1;
end
else if(pcr_st==3'b101) begin
if(TF2_EN) begin
if(PCR_ERR) begin
pcr_st <= 3'b111;
PCRNxtFr <= 1;
// pcr_fnum <= pcr_fnum + 1;
end
else begin
pcr_st <= 3'b000;
end
end
end
else if(pcr_st==3'b111) begin
if(PCREn)
pcr_st <= 3'b001;
else
pcr_st <= 3'b111;
end
else begin
rdpcr_en <= 1;
end
end
PCRS1 :
begin
if(pcr_st == 3'b011)
SPCR0 <= 1;
SRAM_RD <= 0;
end
PCRS2 :
begin
SPCR0 <= 0;
SPCR1 <= 0;
SPCR2 <= 0;
SetFNUM <= 0;
end
PCRS3 :
begin
SRAM_RD <= 1;
end
PCRS4 :
begin
rdpcr_en <= 0;
case (pcr_st)
3'b001 :
begin
if(pcrbuf[5]==1'b1) begin
pcr_st <= 3'b010;
PCRIncEn <= 1;
end
else begin
pcr_st <= 3'b111;
PCRNxtFr <= 1;
pcr_fnum <= pcr_fnum + 1;
end
end
3'b010 :
begin
if(pcrbuf[20]==1'b1) begin
pcr_st <= 3'b011;
SetData <= pcrbuf[15:0];
PCRIncEn <= 1;
end
else begin
pcr_st <= 3'b111;
PCRNxtFr <= 1;
pcr_fnum <= pcr_fnum + 1;
end
end
3'b011 :
begin
SetData <= pcrbuf[31:16];
pcr_st <= 3'b100;
end
default :
begin
pcr_st <= pcr_st;
end
endcase
end
PCRS5 :
begin
SPCR1 <= 0;
SetData <= pcrbuf[15:0];
end
PCRS6 :
begin
SPCR2 <= 1;
end
PCRS7 :
begin
SPCR2 <= 0;
PCRNxtFr <= 1;
SetData <= pcr_fnum;
end
PCRS8 :
begin
SetFNUM <= 1;
pcr_fnum <= pcr_fnum;
PCRNxtFr <= 0;
// pcr_st <= 0;
set_first_pcr <= 0;
if(set_first_pcr)
pcr_st <= 0;
else
pcr_st <= 3'b101;
end
WAIT_DEN :
begin
TxIncEn <= 0;
WrIncEn <= 0;
WrNxtFr <= 0;
PCRIncEn <= 0;
PCRNxtFr <= 0;
sd_rd_en <= 0;
rdpcr_en <= 0;
SPCR0 <= 0;
SPCR1 <= 0;
SPCR2 <= 0;
SetFNUM <= 0;
SRAM_WR <= 1'b1;
SRAM_RD <= 1'b1;
SRAM_FRESH <= 1'b1;
if(TCNT==6'd2 && Send_0Frame)
Send_0Frame <= 0;
end
endcase
end
endmodule
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