comppid.v

华大机顶盒源码(包括所有源代码).rar

module CompPID( CLKM, ResetN, // ResetN = ResetN & !K
                //input 
                Rx_PID, Info_PID, Video_PID, Audio_PID,
                PIDT_DB, CompDZTS_en, 
                //output 
                FValid, bInfo, bProg, bDZTS, CompDZTS_end,
                PIDT_RAddr, PIDT_RD
                );

input CLKM;
input ResetN;
        
input [12:0] Rx_PID;
input [12:0] Info_PID;
input [12:0] Video_PID;
input [12:0] Audio_PID;
input [7:0]  PIDT_DB;
input        CompDZTS_en;

output       FValid;
output       bInfo;
output       bProg;
output       bDZTS;
output       CompDZTS_end;
output [5:0] PIDT_RAddr;
output       PIDT_RD;

reg          FValid;
reg          bInfo;
reg          bProg;
reg          bDZTS;
reg          CompDZTS_end;
reg [5:0]    PIDT_RAddr;
reg          PIDT_RD;

reg [5:0]    CurState;

parameter Idle = 6'b000001, 
          RdPIDHB = 6'b000010, 
          CompPIDHB = 6'b000100, 
          RdPIDLB = 6'b001000, 
          CompPIDLB = 6'b010000,
          CompEnd = 6'b100000;

always @(ResetN or Rx_PID or Info_PID or Video_PID or Audio_PID)
if(!ResetN) begin
	bInfo = 0;
	bProg = 0;
	FValid = 0;
end
else begin
        if(Rx_PID==13'h1FFF) begin
        	FValid = 0;
        	bInfo = 0;
		bProg = 0;
        end
	else if(Rx_PID==Info_PID) begin
        	FValid = 1;
		bInfo = 1;
		bProg = 0;
	end
	else if((Rx_PID==Video_PID) || (Rx_PID==Audio_PID)) begin
        	FValid = 1;
		bInfo = 0;
		bProg = 1;
	end
	else begin
        	FValid = 1;
		bInfo = 0;
		bProg = 0;
	end
end

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	CurState <= Idle;
	bDZTS <= 0;
	CompDZTS_end <= 0;
	PIDT_RAddr <= 6'h00;
	PIDT_RD <= 0;
end   
else begin
	case (CurState)
	Idle : 
	begin
		bDZTS <= 0;
		CompDZTS_end <= 0;
		PIDT_RAddr <= 6'h00;
		PIDT_RD <= 0;
		if(CompDZTS_en)
		begin
			CurState <= RdPIDHB;
		end	          
	end
	RdPIDHB :
	begin
		PIDT_RD <= 1;
		CurState <= CompPIDHB;
	end
	CompPIDHB :
	begin
		PIDT_RD <= 0;
		if(PIDT_DB[7]==0 || PIDT_RAddr==6'h30) begin
			CurState <= CompEnd;
		end
		else if(PIDT_DB[6:5]==2'b00 && PIDT_DB[4:0]==Rx_PID[12:8]) begin
			PIDT_RAddr <= PIDT_RAddr + 1;
			CurState <= RdPIDLB;
		end
		else begin
			PIDT_RAddr <= PIDT_RAddr + 2;
			CurState <= RdPIDHB;
		end
	end
	RdPIDLB :
	begin
		PIDT_RD <= 1;
		CurState <= CompPIDLB;
	end
	CompPIDLB :
	begin
		PIDT_RD <= 0;
		if(PIDT_DB==Rx_PID[7:0]) begin
			bDZTS <= 1;
			CurState <= CompEnd;
		end
		else begin
			PIDT_RAddr <= PIDT_RAddr + 1;
			CurState <= RdPIDHB;
		end
	end
	CompEnd : 
	begin
		CompDZTS_end <= 1;
		if(CompDZTS_en==0)
			CurState <= Idle;
	end   
	default :
	begin
		CurState <= Idle;		
	end
	endcase
end
                
endmodule