📄 dzfifo.v
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`include "rxmodule.v"
`include "txmodule.v"
`include "kswitch.v"
`include "addrreg.v"
`include "csm1.v"
`include "pcrctl.v"
`include "pcrreg.v"
`include "div.v"
`include "irmodule.v"
`include "dvbuf.v"
module dzfifo(ResetN, CLKM,
MDI, IDVALID, IFSYNC, ISFSYNC,
MDO, ODVALID, OFSYNC,
K,ProNum, LPEND,
//SDRAM
SRAM_DI1,SRAM_DI2, SRAM_DO1, SRAM_DO2, SRAM_A, SRAM_CSA, SRAM_WR, SRAM_RD,SRAM_FRESH,
SD_BURST_LEN, SD_DATA_ENA, SD_RD_ENA,
//BlkTable
BlkIndex, BlkData, BlkValid, BlkStb, TSEG, SegWrEn,
SegWrIndex, ReadSEG,SegRdEn, SegRdIndex,
SegTxEn, SegTxIndex,
BLK0VALID, BLK1VALID ,RSEG, CLK1M5,CLK90K,ContWR,
//IR
IR, IR_EN,
//debug
RxMux, RxData, RxFSYNC, RxDEN, FValid, FirstFr, EndFr,TxEn,
PCRn,endframe,pcr_st,rda,err, pcrerr,endferr,
D0,TxDataReq
);
input ResetN;
input CLKM;
input K;
input [1:0] ProNum;
input [7:0] MDI;
input IDVALID;
input IFSYNC;
input ISFSYNC;
input [7:0] SRAM_DI1;
input [7:0] SRAM_DI2;
input [3:0] SD_BURST_LEN;
input SD_DATA_ENA;
input SD_RD_ENA;
input SegWrEn;
input [4:0] SegWrIndex;
input SegRdEn;
input [4:0] SegRdIndex;
input SegTxEn;
input [4:0] SegTxIndex;
input BLK0VALID;
input BLK1VALID;
input CLK1M5;
input CLK90K;
//input no_blk_av;
output [7:0] MDO;
output ODVALID;
output OFSYNC;
output [23:0] SRAM_A;
output [7:0] SRAM_DO1;
output [7:0] SRAM_DO2;
output [1:0] SRAM_CSA;
output SRAM_WR;
output SRAM_RD;
output SRAM_FRESH;
output LPEND;
output IR;
output IR_EN;
output [4:0] BlkIndex;
output [6:0] BlkData;
output BlkValid;
output BlkStb;
output [6:0] TSEG;
output [6:0] RSEG;
output [6:0] ReadSEG;
output ContWR;
//debug
output RxMux;
output [15:0] RxData;
output RxFSYNC, RxDEN, FValid, FirstFr, EndFr,endframe;
output TxEn;
output [32:0] PCRn;
output [2:0] pcr_st;
output [3:0] rda;
output err;
output pcrerr;
output endferr;
//output testbit;
//output pcrtestbit;
output [7:0] D0;
output TxDataReq;
wire RxMux;
wire [15:0] RxData ;
wire RxFSYNC;
wire RxDEN;
wire FValid;
wire FirstFr;
wire EndFr; //test
wire FIFO_DVALID;
wire FIFO_FSYNC;
wire [7:0] FIFO_MDO;
wire [15:0] TxData;
wire TxFSYNC;
wire TxWrEn;
wire TxAddr;
wire TxEn;
wire TxDataReq;
wire [32:0] PCRn;
wire NxtPCRn;
wire Send_0Frame;
wire [32:0] Tsys; // test
wire PCRnV;
wire RdEnd;
wire RdEndOut;
wire [1:0] bufcnt;
wire SPCR0;
wire SPCR1;
wire SPCR2;
wire SetFNum;
wire [15:0] SetData;
wire SetPCREn;
wire [32:0] PCR12;
wire [11:0] FNUM;
wire [32:0] TF;
wire DivEn;
wire TF_En;
wire StartEn;
wire SendIR;
wire [32:0] PCR2; // test
wire [32:0] PCR3; // test
wire [24:0] SegRdAddr;
wire [24:0] SegWrAddr;
wire [24:0] SegTxAddr;
wire PAUSE;
wire PLAYEND;
wire [6:0] MAX_SEG;
wire [25:0] SRAM_AD;
wire [1:0] Mem_Sel;
wire [15:0] SRAM_DI = {SRAM_DI2, SRAM_DI1};
wire [15:0] SRAM_DO;
assign SRAM_DO1 = SRAM_DO[7:0];
assign SRAM_DO2 = SRAM_DO[15:8];
assign MAX_SEG = 7'd125;
assign Mem_Sel = 2'b01;
assign PAUSE = 1'b0;
assign PLAYEND = 1'b0;
assign SRAM_A[23:0] = SRAM_AD[23:0];
assign SRAM_CSA = SRAM_AD[25:24];
wire [7:0] MDI1;
assign MDI1[0] = MDI[0] ^ ISFSYNC;
assign MDI1[1] = MDI[1] ^ ISFSYNC;
assign MDI1[2] = MDI[2] ^ ISFSYNC;
assign MDI1[3] = MDI[3] ^ ISFSYNC;
assign MDI1[4] = MDI[4] ^ ISFSYNC;
assign MDI1[5] = MDI[5] ^ ISFSYNC;
assign MDI1[6] = MDI[6] ^ ISFSYNC;
assign MDI1[7] = MDI[7] ^ ISFSYNC;
//debug
wire [3:0] pcr_rdatest;
assign rda = pcr_rdatest;
//debugend
wire rst = ResetN & ~K;
wire idv;
RxModule U1(.RESETN(ResetN),
.CLKM(CLKM),
.ProNum(ProNum),
.MDI(MDI1),
.VALIDI(idv),//IDVALID),
.FSYNCI(IFSYNC),
.mux(RxMux),
.DATA(RxData),
.FSYNCV(RxFSYNC),
.DEN(RxDEN),
.RSEG(RSEG),
.FValid(FValid),
.FirstFr(FirstFr),
.EndFr(EndFr),
.err(err),
// .testbit(testbit),
.D0(D0),
.bufcnt(bufcnt)
);
KSwitch U2( .K(K),
.CLKM(CLKM),
.DI(MDI1),
.VALIDI(IDVALID),
.FSYNCI(IFSYNC),
.DO(MDO),
.VALIDO(ODVALID),
.FSYNCO(OFSYNC),
.FIFO_MDO(FIFO_MDO),
.FIFO_DVALID(FIFO_DVALID),
.FIFO_FSYNC(FIFO_FSYNC)
);
TxModule U3( .ResetN(rst),
.CLKM(CLKM),
.CLK1M5(CLK1M5),
.IData(TxData),
.IFSYNC(TxFSYNC),
.WrEn(TxWrEn),
.Addr(TxAddr),
.TxEn(TxEn),
.DataReq(TxDataReq),
.OData(FIFO_MDO),
.ODVALID(FIFO_DVALID),
.OFSYNC(FIFO_FSYNC)
);
PCRCtl U4( .ResetN(rst),
.CLKM(CLKM),
.CLK90K(CLK90K),
.PCRn(PCRn),
.NxtPCRn(NxtPCRn),
.Fsync(TxFSYNC),
.Send_0SEG(Send_0Frame),
.TxEn(TxEn),
.Tsys(Tsys), // test
.PCRnV(PCRnV),
.RdEnd(RdEndOut)
);
PcrReg U5( .ResetN(rst),
.CLKM(CLKM),
.PCRn(PCRn),
.NxtPCRn(NxtPCRn),
.SPCR0(SPCR0),
.SPCR1(SPCR1),
.SPCR2(SPCR2),
.SetFNum(SetFNum),
.IData(SetData),
.SetPCREn(SetPCREn),
.PCR12(PCR12),
.FNUM(FNUM),
.TF(TF),
.DivEn(DivEn),
.TF_En(TF_En),
.PCR2(PCR2), // test
.PCR3(PCR3), // test
.PCRnV(PCRnV),
.RdEndIn(RdEnd),
.RdEndOut(RdEndOut),
.pcrerr(pcrerr)
);
div U6( .ResetN(rst),
.CLKM(CLKM),
.dividend(PCR12),
.divisor(FNUM),
.quotient(TF),
.DivEn(DivEn),
.Quo_Valid(TF_En)
);
csm1 U7( .ResetN(rst),
.CLKM(CLKM),
//RxModule
.RxData(RxData),
.FValid(FValid),
.FirstFr(FirstFr),
.RSEG(RSEG),
.RxFSYNC(RxFSYNC),
.RxDEN(RxDEN),
.RxMux(RxMux),
//TxModule
.TxData(TxData),
.TxFSYNC(TxFSYNC),
.Send_0Frame(Send_0Frame),
.TxDataReq(TxDataReq),
.TxWrEn(TxWrEn),
.TxAddr(TxAddr),
//PCRREG
.SPCR0(SPCR0),
.SPCR1(SPCR1),
.SPCR2(SPCR2),
.SetFNUM(SetFNum),
.SetData(SetData),
.SetPCREn(SetPCREn),
.RdEnd(RdEnd),
//SDRAM controller
.SRAM_DI(SRAM_DI),
.SRAM_DO(SRAM_DO),
.SRAM_WR(SRAM_WR),
.SRAM_RD(SRAM_RD),
.SRAM_FRESH(SRAM_FRESH),
.SRAM_AD(SRAM_AD),
.SD_RD_ENA(SD_RD_ENA),
.SD_BURST_LEN(SD_BURST_LEN),
.SD_DATA_ENA(SD_DATA_ENA),
//BLKREG
.BlkIndex(BlkIndex),
.BlkData(BlkData),
.BlkValid(BlkValid),
.BlkStb(BlkStb),
.TSEG(TSEG),
.ReadSEG(ReadSEG),
.SegWrEn(SegWrEn),
.SegWrIndex(SegWrIndex),
.SegWrAddr(SegWrAddr),
.SegRdEn(SegRdEn),
.SegRdIndex(SegRdIndex),
.SegRdAddr(SegRdAddr),
.SegTxEn(SegTxEn),
.SegTxIndex(SegTxIndex),
.SegTxAddr(SegTxAddr),
.BLK0VALID(BLK0VALID),
.BLK1VALID(BLK1VALID),
//irmodule
.StartEn(StartEn),
.SendIR(SendIR),
//system
.MAX_SEG(MAX_SEG),
.PAUSE(PAUSE),
.PLAYEND(PLAYEND),
.LPEND(LPEND),
.ContWR(ContWR),
//debug
.endframe(endframe),
.pcr_st(pcr_st),
.pcr_rdatest(pcr_rdatest),
.endferr(endferr)//,
// .pcrtestbit(pcrtestbit)
);
AddrReg U8 ( .ResetN(rst),
.CLKM(CLKM),
.RdIndex(SegRdIndex),
.WrIndex(SegWrIndex),
.TxIndex(SegTxIndex),
.Mem_Sel(Mem_Sel),
.RdAddr(SegRdAddr),
.WrAddr(SegWrAddr),
.TxAddr(SegTxAddr)
);
IRmodule U9( .ResetN(rst),
.CLKM(CLKM),
.SendEn(SendIR),
.ir(IR),
.ir_en(IR_EN),
.Start(StartEn)
);
dvbuf U10( .ResetN(ResetN),
.CLKM(CLKM),
.VALIDI(IDVALID),
.DVO(idv)
);
endmodule
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