pcrctl.v

华大机顶盒源码(包括所有源代码).rar

module PCRCtl( ResetN, CLKM, CLK90K, 
               PCRn,NxtPCRn, 
               Fsync, Send_0SEG,
               PCRnV, RdEnd, Pause,
               TxEn,
               //debug
               SetTsys, test
               );

input ResetN;            //系统复位信号，来自FPGA的P49脚&(!K)
input CLKM;              //系统主时钟， 来自FPGA的P77脚
input CLK90K;            //90kHz时钟信号，来自CLKMOD.CLK90K

input [32:0] PCRn;       //PCRCtl模块同其他两个模块的接口信号，信号名PCRn
input        PCRnV;      //调试信号，空脚，对应PCRM模块输出端PCRnV 
input        Fsync;      //发送帧同步信号，来自CSM.TxFsync,对应PCRM模块输入端TxFsync   
input        Send_0SEG;  //发送第0帧指示，来自CSM.Send_0Frame,对应PCRM模块输入端Send_0Frame 
input        RdEnd;      //PCRCtl模块同其他两个模块的接口信号，信号名RdEndOut 
input        Pause;      //暂停播放信号，来自I2CTOP.Pause,对应PCRM模块输入端Pause 

output NxtPCRn;          //调试信号，空脚，,对应PCRM模块输出端NxtPCRn
output TxEn;             //节目数据发送允许，作为TXMODULE.ProgTxEn输入,对应PCRM模块输出端ProgTxEn  

//debug
output SetTsys;          //调试信号，空脚，对应PCRM模块输出端SetTsys  
output test;             //调试信号，空脚，对应PCRM模块输出端test  
reg    test;

reg TxEn;
reg SetTsys;
reg NxtPCRn;

wire [32:0] Tsys;

TsysCnt U1(.ResetN(ResetN),
           .CLKM(CLKM),
           .CLK90K(CLK90K),
           .SetTsys(SetTsys),
           .PCRI(PCRn),
           .TSYS(Tsys)
          );

always @(posedge CLKM or negedge ResetN)
    begin
        if(!ResetN) 
            begin
                TxEn <= 0;
                SetTsys <= 0;
                NxtPCRn <= 0;      
                test <= 0;
            end
        else
            if(RdEnd)
                begin
                    TxEn <= 1;
                    SetTsys <= 0;
                    NxtPCRn <= 0;
                    test <= 0;
                end
            else 
                if(!Fsync) 
                    begin
                        TxEn <= TxEn;
                        SetTsys <= 0;
                        NxtPCRn <= 0;
                        test <= 0;
                    end 
                else 
                    if(Pause) 
                        begin
                            TxEn <= 0;
                            SetTsys <= 0;
                            NxtPCRn <= 0;
                            test <= 0;
                        end
                    else 
                        if(!NxtPCRn)  
                            begin
//   else if(!NxtPCRn && Fsync) begin   
                                if(!PCRnV)
                                    begin
                                        TxEn <= 0;
                                        SetTsys <= 0;
                                        NxtPCRn <= 0;         
                                        test <= 0;
                                    end
                                else 
                                    if(Send_0SEG) 
                                        begin
                                            TxEn <= 1;
                                            SetTsys <= 1;
                                            NxtPCRn <= 1;
                                            test <= 0;
                                        end
                                    else 
                                        begin
                                            if(Tsys<PCRn) 
                                                begin
                                                    TxEn <= 0;
                                                    SetTsys <= 0;
                                                    NxtPCRn <= 0;
                                                    test <= 1;
                                                end 
                                            else 
                                                if(Tsys==PCRn) 
                                                    begin
                                                        TxEn <= 1;
                                                        SetTsys <= 0;
                                                        NxtPCRn <= 1;
                                                        test <= 0;
                                                    end 
                                                else 
                                                    begin
                                                        TxEn <= 1;
                                                        SetTsys <= 1;
                                                        NxtPCRn <= 1;
                                                        test <= 0;
                                                    end
                                        end
                            end 
                        else 
                            begin
                                TxEn <= TxEn;
                                SetTsys <= 0;
                                NxtPCRn <= NxtPCRn;
                                test <= test;
                            end
    end

endmodule

module TsysCnt(ResetN, CLKM, CLK90K, 
               SetTsys, PCRI, TSYS);

input ResetN;
input CLKM;
input CLK90K;
input SetTsys;
input [32:0] PCRI;

output [32:0] TSYS;

reg [32:0] TSYS;

reg CLK90K_reg1;
reg CLK90K_reg2;

wire CLK90K_pg;

assign CLK90K_pg = CLK90K_reg1 & ~CLK90K_reg2;

always @(posedge CLKM or negedge ResetN)
    if(!ResetN) 
        begin
            CLK90K_reg1 <= 0;
            CLK90K_reg2 <= 0;
        end 
    else 
        begin
            CLK90K_reg1 <= CLK90K;
            CLK90K_reg2 <= CLK90K_reg1;
        end

always @(posedge CLKM or negedge ResetN)
    if(!ResetN)  
        TSYS <= 0;
    else 
        if(SetTsys)   
            TSYS <= PCRI;
        else 
            if(CLK90K_pg)   
                TSYS <= TSYS + 1;
            else   
                TSYS <= TSYS;

endmodule