savesegreg.v

华大机顶盒源码(包括所有源代码).rar

module SaveSegReg( CLKM, ResetN,
                   //input
                   Init_Mem_End, RegBusy, RxNewSeg, Seg_Num,
                   EndAddr, RT_RDB, TxSeg,
                   //output
                   CompNewSeg_End, 
                   StartAddr, Save_En, 
                   RT_WDB, RT_WEN, RT_CLK, RT_ADDR, comp_oper
                 );
                 
input CLKM;
input ResetN;

input        Init_Mem_End;
input        RegBusy;
input        RxNewSeg;
input [11:0]  Seg_Num;
input [27:0] EndAddr;
input [7:0]  RT_RDB;
input [11:0]  TxSeg;

output        CompNewSeg_End;
output [15:0] StartAddr;
output        Save_En;
output [7:0]  RT_WDB;
output        RT_WEN;
output        RT_CLK;
output [9:0]  RT_ADDR;
output        comp_oper;

reg           CompNewSeg_End;
reg    [15:0] StartAddr;
reg           Save_En;
reg    [7:0]  RT_WDB;
reg           RT_WEN;
reg           RT_CLK;
reg    [9:0]  RT_ADDR;
reg           comp_oper;
reg    [11:0]  CurSegNum;
reg    [11:0] Max_Seg;

reg [4:0] CurState;

reg [6:0]     CurWrBlk;
parameter Idle     = 5'b00000,
	  WrPreEA1 = 5'b00001, WrPreEA2 = 5'b00010, WrPreEA3 = 5'b00011, WrPreEA4 = 5'b00100,
	  WrPreEA5 = 5'b00101, WrPreEA6 = 5'b00111, WrPreEA7 = 5'b01000, WrPreEA8 = 5'b01001,
	  Comp1    = 5'b01010, RdRT1    = 5'b01011, RdRT2    = 5'b01100, RdRT3    = 5'b01101, 
	  RdRT4    = 5'b01110, RdSA1    = 5'b01111, RdSA2    = 5'b10000, RdSA3    = 5'b10001, 
	  RdSA4    = 5'b10010, WrNewSegNum1 = 5'b10011, CompEnd = 5'b10100, 
	  WaitNxtNewSeg = 5'b10101, WrCurSeg1 = 5'b10110, WrCurSeg2 = 5'b10111,
	  WrCurSeg3 = 5'b11000, WrCurSeg4 = 5'b11001;

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	CompNewSeg_End <= 0;
	StartAddr <= 0;
        Save_En <= 0;
	RT_WDB <= 0;
	RT_WEN <= 0;
	RT_CLK <= 0;
	RT_ADDR <= 0;
	comp_oper <= 0;
        CurWrBlk <= 0;
	CurState <= Idle;
        CurSegNum <= 0;
	Max_Seg <= 0;
end
else begin
	case (CurState)
	Idle : 
	begin
		CompNewSeg_End <= 0;
		StartAddr <= 0;
		Max_Seg <= 0;
		if(Init_Mem_End)
			Save_En <= 1;
		else
			Save_En <= 0;
		RT_WDB <= 0;
		RT_WEN <= 0;
		RT_CLK <= 0;
		RT_ADDR <= 0;
		CurWrBlk <= 0;
		if(RxNewSeg && !RegBusy) begin
			comp_oper <= 1;
			CurState <= WrCurSeg1;
		end
		else begin
			comp_oper <= 0;
			CurState <= Idle;
		end
	end    

        WrCurSeg1 :
        begin
        	RT_ADDR[9:3] <= CurWrBlk;
        	RT_ADDR[2:0] <= 3'b000;
        	RT_WDB <= CurSegNum[11:4];
		RT_WEN <= 1;
		RT_CLK <= 0;
		CurState <= WrCurSeg2;		
        end
        WrCurSeg2 :
        begin
        	RT_CLK <= 1;
        	CurState <= WrCurSeg3;
        end
        WrCurSeg3 :
        begin
        	RT_ADDR[2:0] <= 3'b001;
        	RT_WDB <= {CurSegNum[3:0],4'b0000};
		RT_CLK <= 0;
		CurState <= WrCurSeg4;		
        end
        WrCurSeg4 :
        begin
        	RT_CLK <= 1;
        	CurState <= WrPreEA1;
        end
        
//--------------------------Write PreSegment End Address------------------//		
	WrPreEA1 :
	begin
//		RT_ADDR[7:3] <= CurWrBlk;
		RT_ADDR[2:0] <= 3'b100;
		RT_WDB <= EndAddr[7:0];
//		RT_WEN <= 1;
		RT_CLK <= 0;
		CurState <= WrPreEA2;
	end
	WrPreEA2 :
	begin
		RT_CLK <= 1;
		CurState <= WrPreEA3;		
	end
	WrPreEA3 :
	begin
		RT_ADDR[2:0] <= 3'b101;
		RT_WDB <= EndAddr[15:8];
		RT_CLK <= 0;
		CurState <= WrPreEA4;
	end
	WrPreEA4 :
	begin
		RT_CLK <= 1;
		CurState <= WrPreEA5;		
	end
	WrPreEA5 :
	begin
		RT_ADDR[2:0] <= 3'b110;
		RT_WDB <= EndAddr[23:16];
		RT_CLK <= 0;
		CurState <= WrPreEA6;
	end
	WrPreEA6 :
	begin
		RT_CLK <= 1;
		CurState <= WrPreEA7;		
	end
	WrPreEA7 :
	begin
		RT_ADDR[2:0] <= 3'b111;
		RT_WDB <= {4'b0000, EndAddr[27:24]};
		RT_CLK <= 0;
		CurState <= WrPreEA8;
	end
	WrPreEA8 :
	begin
		RT_CLK <= 1;
		CurState <= Comp1;
	end

//-------------------Compare New Segment-----------------//
	Comp1 :
	begin
		RT_CLK <= 0;       
		RT_WEN <= 0;
		if(Seg_Num<=TxSeg) begin
			Save_En <= 0;
			CurState <= CompEnd;		
		end
		else begin
			RT_ADDR <= 0;
			CurWrBlk <= 0;
			RT_WDB <= 0;
			CurState <= RdRT1;
                end
	end 
	
	RdRT1 :
	begin
		RT_CLK <= 1;
		CurState <= RdRT2;		
	end

	RdRT2 : 
	begin
		RT_CLK <= 0;
		if((RT_RDB==8'hFF) || (RT_ADDR[9:3]==7'h7F)) begin
			if(Seg_Num<Max_Seg) begin
				Save_En <= 1;
				RT_ADDR[9:3] <= CurWrBlk;
				RT_ADDR[2:0] <= 3'b010;
				CurState <= RdSA1;
			end
			else begin
				Save_En <= 0;
				CurState <= CompEnd;
			end
		end
		else begin
			RT_WDB <= RT_RDB;
			RT_ADDR[2:0] <= 3'b001;
			CurState <= RdRT3;			
		end
	end
	
/*	RdRT2 :
	begin
		RT_CLK <= 0;
		if((RT_RDB==8'hFF) || (RT_ADDR[9:3]==7'h7F)) begin
			if(Seg_Num<RT_WDB) begin
				Save_En <= 1;
				RT_ADDR[9:3] <= CurWrBlk;
				RT_ADDR[2:0] <= 3'b010;
				CurState <= RdSA1;
			end
			else begin
				Save_En <= 0;
				CurState <= CompEnd;
			end
		end
		else if(RT_RDB==Seg_Num) begin
			Save_En <= 0;
			CurState <= CompEnd;
		end
		else if(RT_RDB>RT_WDB) begin
			CurWrBlk <= RT_ADDR[9:3];
			RT_WDB <= RT_RDB;
			RT_ADDR[9:3] <= RT_ADDR[9:3]+1;
			RT_ADDR[2:0] <= 3'b000;
			CurState <= RdRT1;			
		end
		else begin
			RT_ADDR[9:3] <= RT_ADDR[9:3]+1;
			RT_ADDR[2:0] <= 3'b000;
			CurState <= RdRT1;			
		end
	end	
*/	
	RdRT3 : begin
		RT_CLK <= 1;
		CurState <= RdRT4;			
	end	
	
	RdRT4 : begin
		RT_CLK <= 0;
		if( {RT_WDB, RT_RDB[7:4]} == Seg_Num ) begin
			Save_En <= 0;
			CurState <= CompEnd;
		end
		else if( {RT_WDB, RT_RDB[7:4]} > Max_Seg ) begin
			CurWrBlk <= RT_ADDR[9:3];
			Max_Seg <= {RT_WDB, RT_RDB[7:4]};
			RT_ADDR[9:3] <= RT_ADDR[9:3]+1;
			RT_ADDR[2:0] <= 3'b000;
			CurState <= RdRT1;			
		end
		else begin
			RT_ADDR[9:3] <= RT_ADDR[9:3]+1;
			RT_ADDR[2:0] <= 3'b000;
			CurState <= RdRT1;			
		end
	end
	
	
//----------------Read Start Addr-----------------------//	
	RdSA1 :
	begin
		RT_CLK <= 1;
		CurState <= RdSA2;						
	end	
	RdSA2 :
	begin
		RT_CLK <= 0;
		StartAddr[7:0] <= RT_RDB;
		RT_ADDR[2:0] <= 3'b011;
		CurState <= RdSA3;
	end
	
	RdSA3 :
	begin
		RT_CLK <= 1;
		CurState <= RdSA4;		
	end
	RdSA4 :
	begin
		RT_CLK <= 0;
		StartAddr[15:8] <= RT_RDB;
		RT_ADDR[2:0] <= 0;
		CompNewSeg_End <= 1;
		comp_oper <= 0;
		CurSegNum <= Seg_Num;
		CurState <= WaitNxtNewSeg;
	end
	CompEnd :
	begin
		RT_CLK <= 0;
		CompNewSeg_End <= 1;
		comp_oper <= 0;
		CurState <= WaitNxtNewSeg;
	end
	WaitNxtNewSeg :
	begin
		if(!RxNewSeg)
			CompNewSeg_End <= 0;
		RT_WDB <= 0;
		RT_WEN <= 0;
		RT_CLK <= 0;
		RT_ADDR <= 0;
		Max_Seg <= 0;
		if(RxNewSeg && !CompNewSeg_End && !RegBusy) begin
			comp_oper <= 1;
			if(Save_En)
				CurState <= WrCurSeg1;
			else
				CurState <= Comp1;
		end
	end
	default :
	begin
		CurState <= Idle;
	end
	endcase
end


endmodule