gettxsegaddr.v

华大机顶盒源码(包括所有源代码).rar

module GetTxSegAddr( CLKM, ResetN, 
                     //input 
                     RegBusy, TxSeg, FindTxSegA_En, 
                     RT_RDB, RDPCR_EN,
                     //output
                     SegAddr, FindTxSegA_End,
                     tx_oper, RT_WDB, RT_CLK, RT_WEN, RT_ADDR
                   );   

input       CLKM;
input       ResetN;

input       RegBusy;
input [11:0] TxSeg;
input       FindTxSegA_En;
input [7:0] RT_RDB;
input       RDPCR_EN;

output [27:0] SegAddr;
output        FindTxSegA_End;
output        tx_oper; 
output [7:0]  RT_WDB;
output        RT_CLK;
output        RT_WEN;
output [9:0]  RT_ADDR;

reg    [27:0] SegAddr;
reg           FindTxSegA_End;
reg           tx_oper;
reg    [7:0]  RT_WDB;
reg           RT_CLK;
reg           RT_WEN;
reg    [9:0]  RT_ADDR;

reg    [4:0]  CurState;

wire [11:0] Pre_Tx_Seg = TxSeg - 1;

parameter Idle      = 5'd0  , RdSegNum1    = 5'd1  , RdSegNum2    = 5'd2  , RdSegNum3   = 5'd3  , 
          RdSegNum4 = 5'd4  , RdSegNum5    = 5'd5  , RdSegNum6    = 5'd6  , RdSegNum7   = 5'd7  , 
          RdSegNum8 = 5'd8  , RdSA1        = 5'd9  , RdSA2        = 5'd10 , RdSA3       = 5'd11 , 
          RdSA4     = 5'd12 , RdTxSAEn     = 5'd13 , RdEA1        = 5'd14 , RdEA2       = 5'd15 , 
          RdEA3     = 5'd16 , RdEA4        = 5'd17 , RdEA5        = 5'd18 , RdEA6       = 5'd19 , 
          RdEA7     = 5'd20 , RdEA8        = 5'd21 , OperEnd      = 5'd22 , ClearPreSeg1 = 5'd23 , 
          ClearPreSeg2 = 5'd24 , ClearPreSeg3 = 5'd25 , 
          ClearPreSeg4 = 5'd26 , WaitRdPCREn = 5'd27 ;
          
always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	SegAddr <= 0;
	FindTxSegA_End <= 0;
	tx_oper <= 0;
	RT_WDB <= 0;
	RT_CLK <= 0;
	RT_WEN <= 0;
	RT_ADDR <= 0;
	CurState <= Idle;
end
else begin
	case (CurState)
		Idle :
		begin
			if(!FindTxSegA_En)
				FindTxSegA_End <= 0;
			SegAddr <= SegAddr;
			RT_WDB <= 0;
			RT_CLK <= 0;
			RT_WEN <= 0;
			RT_ADDR <= 0;
			if(FindTxSegA_En && !RegBusy && !FindTxSegA_End) begin
				tx_oper <= 1;		
				if(TxSeg==0)
					CurState <= ClearPreSeg4;
				else
					CurState <= RdSegNum1;
			end
			else begin
				tx_oper <= 0;
				CurState <= Idle;
			end
		end
		RdSegNum1 :
		begin
			RT_CLK <= 1;	
			CurState <= RdSegNum2;
		end
		RdSegNum2 :
		begin
			RT_CLK <= 0;
		        if(RT_RDB==Pre_Tx_Seg[11:4]) begin
		        	RT_ADDR[2:0] <= 3'b001;
		        	CurState <= RdSegNum3;
		        end
		        else if(RT_RDB==8'hFF) begin
		        	CurState <= ClearPreSeg4;
		        end
			else begin
				RT_ADDR[9:3] <= RT_ADDR[9:3] + 1;
				RT_ADDR[2:0] <= 3'b000;
				CurState <= RdSegNum1;
			end			
		end
		RdSegNum3 :
		begin
			RT_CLK <= 1;
			CurState <= RdSegNum4;
		end
		RdSegNum4 : 
		begin
			RT_CLK <= 0;
			if(RT_RDB[7:4] <= Pre_Tx_Seg[3:0]) begin
				RT_WDB <= 8'hFE;
				RT_WEN <= 1;
				RT_ADDR[2:0] <= 3'b000;
				CurState <= ClearPreSeg1;
			end
			else begin
				RT_ADDR[9:3] <= RT_ADDR[9:3] + 1;
				RT_ADDR[2:0] <= 3'b000;
				CurState <= RdSegNum1;
			end				
		end
		
		
		ClearPreSeg1 :
		begin
			RT_CLK <= 1;
			CurState <= ClearPreSeg2;				
		end
		ClearPreSeg2 :
		begin
			RT_CLK <= 0;
			RT_WDB <= 8'h00;
			RT_ADDR[2:0] <= 3'b001;
			CurState <= ClearPreSeg3;
		end
		ClearPreSeg3 :
		begin
			RT_CLK <= 1;
			CurState <= ClearPreSeg4;				
		end
		ClearPreSeg4 :
		begin
			RT_CLK <= 0;
			RT_WEN <= 0;
			RT_ADDR <= 0; 
			RT_WDB <= 0;
			CurState <= RdSegNum5;
		end
                
                RdSegNum5 :
		begin
			RT_CLK <= 1;	
			CurState <= RdSegNum6;
		end
		RdSegNum6 :
		begin
			RT_CLK <= 0;
			if(RT_RDB==TxSeg[11:4]) begin
				RT_ADDR[2:0] <= 3'b001;
				CurState <= RdSegNum7;
			end
			else if(RT_RDB==8'hFF) begin
				CurState <= WaitRdPCREn;
			end
			else begin
				RT_ADDR[9:3] <= RT_ADDR[9:3] + 1;
				RT_ADDR[2:0] <= 3'b000;
				CurState <= RdSegNum5;
			end
		end		
		RdSegNum7 :
		begin
			RT_CLK <= 1;
			CurState <= RdSegNum8;
		end
		RdSegNum8 :
		begin
			RT_CLK <= 0;
			if(RT_RDB[7:4]==TxSeg[3:0]) begin
				RT_WEN <= 0;
				RT_ADDR[2:0] <= 3'b010;
				CurState <= RdSA1;
			end  
			else begin
				RT_ADDR[9:3] <= RT_ADDR[9:3] + 1;
				RT_ADDR[2:0] <= 3'b000;
				CurState <= RdSegNum5;
			end					
		end
		
		RdSA1 : 
		begin
			RT_CLK <= 1;
			CurState <= RdSA2;
		end
		RdSA2 :
		begin
			RT_CLK <= 0;
			SegAddr[11:0] <= 0;
			SegAddr[19:12] <= RT_RDB;
			RT_ADDR[2:0] <= 3'b011;
			CurState <= RdSA3;
		end
		RdSA3 :
		begin
			RT_CLK <= 1;
			CurState <= RdSA4;
		end
		RdSA4 :
		begin
			RT_CLK <= 0;
			SegAddr[27:20] <= RT_RDB;
			RT_ADDR[2:0] <= 3'b100;
			CurState <= RdTxSAEn;
		end		
		RdTxSAEn :
		begin
			FindTxSegA_End <= 1;
			if(!FindTxSegA_En) 
				CurState <= RdEA1;
		end
		RdEA1 :
		begin
			RT_CLK <= 1;
			CurState <= RdEA2;
		end
		RdEA2 :
		begin
			RT_CLK <= 0;
			SegAddr[7:0] <= RT_RDB;
			RT_ADDR[2:0] <= 3'b101;
			CurState <= RdEA3;
		end
		RdEA3 :
		begin
			RT_CLK <= 1;
			CurState <= RdEA4;
		end
		RdEA4 :
		begin
			RT_CLK <= 0;
			SegAddr[15:8] <= RT_RDB;
			RT_ADDR[2:0] <= 3'b110;
			CurState <= RdEA5;
		end
		RdEA5 :
		begin
			RT_CLK <= 1;
			CurState <= RdEA6;
		end
		RdEA6 :
		begin
			RT_CLK <= 0;
			SegAddr[23:16] <= RT_RDB;
			RT_ADDR[2:0] <= 3'b111;
			CurState <= RdEA7;
		end
		RdEA7 :
		begin
			RT_CLK <= 1;
			CurState <= RdEA8;
		end
		RdEA8 :
		begin
			RT_CLK <= 0;
			SegAddr[27:24] <= RT_RDB[4:0];
			RT_ADDR[2:0] <= 3'b000;
			CurState <= OperEnd;
		end
		OperEnd :
		begin
			FindTxSegA_End <= 0;
			tx_oper <= 0;
			CurState <= Idle;
		end
		WaitRdPCREn :
		begin
			FindTxSegA_End <= 0;
			RT_WDB <= 0;
			RT_CLK <= 0;
			RT_WEN <= 0;
			RT_ADDR <= 0;
			tx_oper <= 0;
			if(RDPCR_EN)
				CurState <= Idle;
		end
		default :
		begin
			CurState <= Idle;
		end
	endcase
end

endmodule