rxmodule.v

华大机顶盒源码(包括所有源代码).rar

module RxModule(RESETN, CLKM,
                //input
                MDI, VALIDI, FSYNCI, DMUX,
                //output 
                DATA, FSYNCV, DEN,RX_PID,
                //debug
                test 
                ); 

input         RESETN;                                   //reset signal,low level is valid.
input         CLKM;                                      //the synchrony clock signal

input [7:0]   MDI;                                       //the input data,8bits
input         VALIDI;                                    //the valid data signal
input         FSYNCI;                                    //the data synchrony signal.
                                                                   //FSYNCI=1,indicate the MDI byte data should save into 
                                                                   //the first buffer unit(buffer0[0] or buffer[1])
input         DMUX;                                     //

output [15:0] DATA;                                 //the output data,16bits 
output        FSYNCV;
output        DEN;
output [12:0]  RX_PID;                             //the pid data output

//debug
output       test;
reg          test;
//debug

reg [7:0]  DBUFF0[0:3];                            //the depth is four ,the word length is 8bits
reg [7:0]  DBUFF1[0:3];
reg        FSYNC1;
reg        FSYNCV;
reg [12:0] RX_PID;

reg        BufSel;                                         //select buffer signal
reg [1:0]  bufcnt;                                       //buffer address counter
reg        buffull;                                         //the flag that the input buffer is full
reg        reg1, reg2;                          

wire [31:0] DBUFF;
wire [31:0] TEMPD;

//wire testbit;

assign DBUFF = BufSel ? ({DBUFF0[0], DBUFF0[1], DBUFF0[2], DBUFF0[3]}):                                    //according to the BufSel,
                          ({DBUFF1[0], DBUFF1[1], DBUFF1[2], DBUFF1[3]});                                                   //select DBUFF0 or DBUFF1
assign TEMPD = BufSel ? ({DBUFF1[0], DBUFF1[1], DBUFF1[2], DBUFF1[3]}): 
                          ({DBUFF0[0], DBUFF0[1], DBUFF0[2], DBUFF0[3]});                         
assign DATA  = DMUX ? DBUFF[15:0] : DBUFF[31:16];
assign DEN   = reg1 & ~reg2;

parameter MAX_SEG = 7'd125;

always @(negedge RESETN or posedge CLKM)
begin
if(!RESETN) begin                                     // RESETN=1,then clear the DBUFF0 and DBUFF1                                                     
   DBUFF0[0] <= 0;
   DBUFF0[1] <= 0;
   DBUFF0[2] <= 0;
   DBUFF0[3] <= 0;   
   DBUFF1[0] <= 0;
   DBUFF1[1] <= 0;
   DBUFF1[2] <= 0;
   DBUFF1[3] <= 0;
end else if(VALIDI) begin
    if(BufSel) begin
       if(FSYNCI)   DBUFF1[0] <= MDI;
       else   DBUFF1[bufcnt] <= MDI;
    end else begin
       if(FSYNCI)  DBUFF0[0] <= MDI;
       else  DBUFF0[bufcnt] <= MDI;
    end
end 
end

always @(negedge RESETN or posedge CLKM)
if(!RESETN) 
    BufSel <= 0;
else if(bufcnt==2'b11 && VALIDI)
    BufSel <= ~BufSel;

always @(negedge RESETN or posedge CLKM)
if(!RESETN) begin
    bufcnt <= 0;
    FSYNC1 <= 0;
    buffull <= 0;
end else if(VALIDI) begin
    if(FSYNCI) begin
       bufcnt <= 2'b01;
       FSYNC1 <= 1;
       buffull <= 0;
    end else if(bufcnt==2'b11) begin
       bufcnt <= 2'b00;
       FSYNC1 <= 0;
       buffull <= 1;
    end else begin
       bufcnt <= bufcnt + 1;
       FSYNC1 <= FSYNC1;
       buffull <= 0;
    end
end

always @(posedge CLKM or negedge RESETN)
if(!RESETN) begin
   reg1 <= 0;
   reg2 <= 0;
end else begin
   reg1 <= buffull;
   reg2 <= reg1;
end

always @(negedge RESETN or posedge CLKM)
if(!RESETN)  FSYNCV <= 0;
else if(bufcnt==2'b11) FSYNCV <= FSYNC1;
else FSYNCV <= FSYNCV;   

always @(negedge RESETN or posedge CLKM)
if(!RESETN)   RX_PID <= 0;
else if(bufcnt==2'b11 && FSYNC1 && !FSYNCV)
    RX_PID <= TEMPD[20:8];
else  RX_PID <= RX_PID;

//debug
always @(negedge RESETN or posedge CLKM)
if(!RESETN)   test <= 0;
else if(bufcnt==2'b11 && FSYNC1 && !FSYNCV)
    if(TEMPD[20:8]==13'h1FFF)
       test <= 0;
    else
       test <= 1;
else  test <= test;


endmodule