div1.v

华大机顶盒源码(包括所有源代码).rar

module div1(ResetN, CLKM, dividend, divisor, quotient, DivEn, Quo_Valid);

input         ResetN;
input         CLKM;

input  [32:0] dividend;
input  [11:0] divisor;
input         DivEn;

output [32:0] quotient;
output        Quo_Valid;

reg [32:0] quotient;
reg [32:0] remainder;
reg [1:0]  cur_st;
reg [5:0]  i;
reg        DivEn_reg;
reg        Quo_Valid;

parameter IDLE = 2'b00, INIT = 2'b01, LSHIFT = 2'b11, COMPARE = 2'b10;

wire DivEn_edge = DivEn & ~DivEn_reg;

always @(posedge CLKM or negedge ResetN)
begin
if(!ResetN) 
  DivEn_reg <= 0;
else
  DivEn_reg <= DivEn;
end

always @(posedge CLKM or negedge ResetN)
begin
if(!ResetN) begin
   quotient <= 0;
   remainder <= 0;
   cur_st <= 0;
   i <= 0;
   Quo_Valid <= 0;
end 
else begin
   case (cur_st)
   IDLE : begin
          if(DivEn_edge)
            cur_st <= INIT;
          else
            cur_st <= IDLE;
          quotient <= quotient;
          remainder <= remainder;
          i <= 0;
          Quo_Valid <= Quo_Valid;
          end
   INIT : begin
          cur_st <= LSHIFT;
          quotient <= dividend;
          remainder <= 0;
          i <= 0;
          Quo_Valid <= 0;
          end
   LSHIFT : begin
            cur_st <= COMPARE;
            quotient[32:1] <= quotient[31:0];
            quotient[0] <= 0;
            remainder[11:1] <= remainder[10:0];
            remainder[0] <= quotient[32];
            i <= i+1;
            Quo_Valid <= 0;
            end
   COMPARE : begin
             if(i==33) begin
               cur_st <= IDLE;
               Quo_Valid <= 1;
             end
             else begin
               cur_st <= LSHIFT; 
               Quo_Valid <= 0;
             end
             if(remainder>=divisor) begin
                remainder <= remainder - divisor;
                quotient[0] <= 1;
             end
             i <= i;
             end
   endcase
end
end

endmodule