txmodule.v

华大机顶盒源码(包括所有源代码).rar

module TxModule( ResetN, CLKM, 
                 //input
                 ProgData, ProgWrEn, ProgAddr, ProgTxEn,
                 EPGData,  EPGWrEn,  EPGAddr,  EPGTxEn, 
                 //output
                 ProgDataReq, EPGDataReq,
                 OData, ODVALID, OFSYNC,
                 //debug
                 Fsync_reg, bufcnt, DataCnt, BufSel,test
                 );

input ResetN;
input CLKM;

input  [15:0] ProgData;
input         ProgWrEn;
input         ProgAddr;
input         ProgTxEn;

input [15:0]  EPGData;
input         EPGWrEn;
input         EPGAddr;
input         EPGTxEn;

output        ProgDataReq;
output        EPGDataReq;

output [7:0]  OData;
output        ODVALID;
output        OFSYNC;

//debug
output [1:0] Fsync_reg;
output [1:0] bufcnt;
output [5:0] DataCnt;
output       BufSel;
output       test;
//debug

reg [7:0] OData;
reg       ODVALID;
reg       DVALID;
reg       OFSYNC;
//reg       ProgDataReq;
//reg       EPGDataReq;

reg [7:0] DBUFF0[0:3];
reg [7:0] DBUFF1[0:3];
reg [1:0] Fsync_reg;
reg [1:0] bufcnt;
reg [1:0] buffull;
reg [2:0] ClkCnt;
reg [5:0] DataCnt;
//reg       SendEPG;
reg       BufSel;

wire [15:0] IData;
wire        IWrEn;
wire        IAddr;
wire        ITxEn;
wire [7:0]  bufdata;

//assign IData = SendEPG ? EPGData : ProgData;
//assign IWrEn = SendEPG ? EPGWrEn : ProgWrEn;
//assign IAddr = SendEPG ? EPGAddr : ProgAddr;
//assign ITxEn = EPGTxEn || ProgTxEn;

//assign bufdata = BufSel ? DBUFF0[bufcnt] : DBUFF1[bufcnt]; 
//assign EPGDataReq = SendEPG & (~buffull[BufSel]) & EPGTxEn;
//assign ProgDataReq = (!SendEPG) & (~buffull[BufSel]) & ProgTxEn;

reg       SendProg;
reg [4:0] DelayCnt;

assign IData = SendProg ? ProgData : EPGData;
assign IWrEn = SendProg ? ProgWrEn : EPGWrEn;
assign IAddr = SendProg ? ProgAddr : EPGAddr;
assign ITxEn = EPGTxEn || ProgTxEn;

assign bufdata = BufSel ? DBUFF0[bufcnt] : DBUFF1[bufcnt]; 
assign EPGDataReq = (!SendProg) & (~buffull[BufSel]) & EPGTxEn & DelayCnt[4];
assign ProgDataReq = SendProg & (~buffull[BufSel]) & ProgTxEn & DelayCnt[4];


/*always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	EPGDataReq <= 0;
	ProgDataReq <= 0;
end
else begin
	EPGDataReq <= SendEPG & (~buffull[BufSel]) & EPGTxEn;
	ProgDataReq <= (!SendEPG) & (~buffull[BufSel]) & ProgTxEn;
end
*/
//debug
assign test = IWrEn && IAddr;
//debug

always @(posedge CLKM or negedge ResetN)
if(!ResetN)	ClkCnt <= 0;
else if(ClkCnt==3'b101)	ClkCnt <= 0;
else	ClkCnt <= ClkCnt + 1;

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	DBUFF0[0] <= 0;
	DBUFF0[1] <= 0;
	DBUFF0[2] <= 0;
	DBUFF0[3] <= 0;
	DBUFF1[0] <= 0;
    	DBUFF1[1] <= 0;
	DBUFF1[2] <= 0;
    	DBUFF1[3] <= 0;
    	Fsync_reg <= 0;
end
else if(IWrEn) begin
    	if(BufSel) begin
    		if(IAddr) begin
			DBUFF1[2] <= IData[15:8];
			DBUFF1[3] <= IData[7:0];
			Fsync_reg[1] <= (DataCnt==0);
		end else begin
			DBUFF1[0] <= IData[15:8];
			DBUFF1[1] <= IData[7:0];
		end
	end
	else begin
		if(IAddr) begin
			DBUFF0[2] <= IData[15:8];
			DBUFF0[3] <= IData[7:0];
			Fsync_reg[0] <= (DataCnt==0);
		end else begin
			DBUFF0[0] <= IData[15:8];
			DBUFF0[1] <= IData[7:0];
		end
	end
end

always @(posedge CLKM or negedge ResetN)
if(!ResetN)
	BufSel <= 0;
else if(buffull[BufSel] && !buffull[~BufSel])
	BufSel <= ~BufSel;

always @(posedge CLKM or negedge ResetN)
if(!ResetN)
	DataCnt <= 0;
else if(IWrEn && IAddr) begin
	if(DataCnt==6'h7)
		DataCnt <= 0;
	else 
		DataCnt <= DataCnt + 1;
end
else begin
	DataCnt <= DataCnt;
end

always @(posedge CLKM or negedge ResetN)
if(!ResetN)
   DelayCnt <= 5'b10000;
else if (IWrEn && IAddr && DataCnt==6'h2E)
   DelayCnt <= 0;
else if (ClkCnt==3'b101) begin
   if ( DelayCnt != 5'b10000)
      DelayCnt <= DelayCnt + 5'b00010; 
end   
   

//always @(posedge CLKM or negedge ResetN)
//if(!ResetN) begin
//	SendEPG <= 0;
//end
//else if(DataCnt==0 && !ProgDataReq) begin
//	if(EPGTxEn)
//		SendEPG <= 1;
//	else
//		SendEPG <= 0;
//        if(ProgTxEn)
//end
//else
//	SendEPG <= SendEPG;

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	SendProg <= 0;
end
else if(DataCnt==0 && !EPGDataReq) begin
	if(ProgTxEn)
		SendProg <= 1;
	else
		SendProg <= 0;
end
else
	SendProg <= SendProg;


always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
   buffull <= 0;
end
else begin
   if(~buffull[BufSel] && IWrEn && IAddr) 
       buffull[BufSel] <= 1;
   if(buffull[~BufSel] && ClkCnt==3'b101 && bufcnt==2'b11) 
       buffull[~BufSel] <= 0;   
end

always @(posedge CLKM or negedge ResetN)
if(!ResetN)
	ODVALID <= 0;
else
	ODVALID <= DVALID;

always @(posedge CLKM or negedge ResetN)
begin
   if(!ResetN) begin
      OData <= 0;
      OFSYNC <= 0;
      DVALID <= 0;
   end
   else if(ClkCnt==3'b101) begin
      if(buffull[~BufSel]/*!TxEnd*/) begin
//          if(Fsync_reg[~BufSel]) begin
//             if(bufcnt==2'b01)
//                OData <= {bufdata[7:5], 5'b00001};//((DBUFF[bufcnt] & 8'b11100001) | 8'b00000001);             
//             else if(bufcnt==2'b10)
                /*if(bufdata[0])
                   OData <= 8'h22;
                else 
                   OData <= 8'h21;*/
//                if(bufdata[2:1]==2'b00) 
//                   OData <= {7'b0000100,bufdata[0]};
//                else if(bufdata[2:1]==2'b01)
//                   OData <= {7'b0000100,bufdata[0]};
//                else if(bufdata[2:1]==2'b10)
//                   OData <= {7'b0001000,bufdata[0]};
//                else 
//                   OData <= bufdata;
                //OData <= ((DBUFF[bufcnt] & 8'b00001001) | 8'b00001000);                          
//             else
//                OData <= bufdata;
//          end
//          else
             OData <= bufdata;
          DVALID <= 1;
          if(bufcnt==2'b00)
             OFSYNC <= Fsync_reg[~BufSel];
          else 
             OFSYNC <= 0;
          if(bufcnt==2'b11) begin
             bufcnt <= 2'b00;
//             TxEnd <= 1;  
          end else begin
             bufcnt <= bufcnt + 1;
//             TxEnd <= 0;
          end
      end
   end
   else begin
      if(ClkCnt==3'b001)
          DVALID <= 0;
//      if(!TxEn)
//         TxEnd <= 0;
   end     
end

endmodule