csm1.v

华大机顶盒源码(包括所有源代码).rar

module csm1(  ResetN, CLKM,  
              //RxModule
              RxData, FValid, FirstFr, RSEG, RxFSYNC, RxDEN,RxMux,
              //TxModule
              TxData, TxFSYNC, Send_0Frame, TxDataReq,TxWrEn, TxAddr,
              //PCRREG
              SPCR0, SPCR1, SPCR2, SetFNUM, SetData,SetPCREn, RdEnd,        
              //SDRAM controller
              SRAM_DI, SRAM_DO, SRAM_WR, SRAM_RD,SRAM_FRESH, SRAM_AD,  
              SD_RD_ENA, SD_BURST_LEN, SD_DATA_ENA,
              //BLKREG
              BlkIndex,BlkData,BlkValid, BlkStb, TSEG, ReadSEG,
              SegWrEn, SegWrIndex, SegWrAddr, 
              SegRdEn, SegRdIndex, SegRdAddr,
              SegTxEn, SegTxIndex, SegTxAddr, 
              BLK0VALID,BLK1VALID,ContWR,
              //irmodule
              SendIR, StartEn,
              //system
              MAX_SEG, PAUSE, PLAYEND, LPEND,
              //debug
              endframe,pcr_st,pcr_rdatest, endferr//,pcrtestbit
//              sd_ra0, sd_wa0,cur_st,
//              Search_0SEG, WR_EN,ContWR,TFRAME,RD_EN,wrfsync,err,
            );
 
input ResetN;
input CLKM;

//RxModule
input [15:0]  RxData;
input         FValid;
input         FirstFr;
input [6:0]   RSEG;
input         RxFSYNC;
input         RxDEN;
output        RxMux;

//TxModule
input         TxDataReq;
output [15:0] TxData;
output        TxFSYNC;
output        Send_0Frame;
output        TxWrEn;
output        TxAddr;

//PCRREG
input         SetPCREn;
output        SPCR0;
output        SPCR1;
output        SPCR2; 
output        SetFNUM; 
output [15:0] SetData; 
output        RdEnd;

//SDRAM controller
input [15:0]  SRAM_DI;
input         SD_RD_ENA;
input [3:0]   SD_BURST_LEN;
input         SD_DATA_ENA;
output [15:0] SRAM_DO;
output        SRAM_WR;
output        SRAM_RD;
output        SRAM_FRESH;
output [25:0] SRAM_AD;
  
//BLKREG
input        SegWrEn;
input [4:0]  SegWrIndex;
input [24:0] SegWrAddr;
input        SegRdEn;
input [4:0]  SegRdIndex;
input [24:0] SegRdAddr;
input        SegTxEn;
input [4:0]  SegTxIndex;
input [24:0] SegTxAddr;

input        BLK0VALID;
input        BLK1VALID;
output [4:0]  BlkIndex;
output [6:0]  BlkData;
output        BlkValid;
output        BlkStb;
output [6:0]  TSEG;
output [6:0]  ReadSEG;
output        ContWR;

//irmodule
input         StartEn;
output        SendIR;

//system
input [6:0]  MAX_SEG;
input        PAUSE;
input        PLAYEND;
output       LPEND;

//debug
output       endframe;
output [2:0] pcr_st;
output [3:0] pcr_rdatest;
output       endferr;              
//output       pcrtestbit;
reg          endferr;

reg        TxFSYNC;
reg        Send_0Frame;
reg        SPCR0;
reg        SPCR1;
reg        SPCR2;
reg        SetFNUM;
reg [15:0] SetData;
reg        RdEnd;
reg        SRAM_WR;
reg        SRAM_RD;
reg        SRAM_FRESH;
reg [4:0]  BlkIndex;
reg [6:0]  BlkData;
reg        BlkValid;
reg        BlkStb;
reg [6:0]  TSEG;
reg [6:0]  ReadSEG;
reg        LPEND;
reg        SendIR;

//internal register
reg        sd_rd_en;
reg        rdpcr_en;
reg [24:0] sd_wa;
reg [24:0] sd_ra;
reg [24:0] pcr_rda;          
reg [11:0] pcr_fnum;
reg [31:0] pcrbuf;

reg        TFRAME;
reg [5:0]  RCNT;
reg [5:0]  TCNT;
reg        WR_EN;
reg        RD_EN;
reg [4:0]  PreSegIndex;
reg        endframe;
reg        Search_0SEG;
reg        WaitWA;
reg        ContWR;
reg        Wait_SegTxEn;
//reg        pcrtestbit;
reg        pcrerr;

reg [2:0]  pcr_st;
reg [5:0]  cur_st;
reg [5:0]  nxt_st;


parameter FRAME_CNT = 6'd47;
parameter IDLE = 6'd0, WRS0 = 6'd1, WRS01 = 6'd2, WRS1 = 6'd3,
          WRS2 = 6'd4, WRS3 = 6'd5, WRS4 = 6'd6,
          WRS5 = 6'd7, WRS6 = 6'd8, WRS7 = 6'd9, 
          WRS8 = 6'd10, RDS0 = 6'd11, RDS1 = 6'd12,
          RDS2 = 6'd13, RDS3 = 6'd14, RDS4 = 6'd15, 
          RDS5 = 6'd16, RDS6 = 6'd17, RDS7 = 6'd18,
          RDS8 = 6'd19, RDS9 = 6'd20, 
          WAIT_DEN = 6'd21,
          REFRESH1 = 6'd22, REFRESH2 = 6'd23,
          REFRESH3 = 6'd39, REFRESH4 = 6'd40,
          PCRS0 = 6'd24, PCRS1 = 6'd25, PCRS2 = 6'd26, 
          PCRS3 = 6'd27, PCRS4 = 6'd28, PCRS5 = 6'd29, 
          PCRS6 = 6'd30, PCRS7 = 6'd31, PCRS8 = 6'd32,
          PCRS9 = 6'd33, PCRS10 = 6'd34, PCRS11 = 6'd35,
          SENDPEND0 = 6'd36, SENDPEND1=6'd37, SENDPEND2=6'd38;


assign   RxMux = SD_DATA_ENA ? SD_BURST_LEN[0] : 0;
assign   TxData = SRAM_DI;
assign   TxWrEn = sd_rd_en ? SD_RD_ENA : 0;
assign   TxAddr = sd_rd_en ? SD_BURST_LEN[0] : 0;
assign   SRAM_DO = RxData;
assign   SRAM_AD[0] = 0;
assign   SRAM_AD[18:1] = rdpcr_en ? pcr_rda[17:0] : (sd_rd_en ? sd_ra[17:0] : sd_wa[17:0]);
assign   SRAM_AD[19] = (~SRAM_FRESH) || (rdpcr_en ? pcr_rda[18] : (sd_rd_en ? sd_ra[18] : sd_wa[18]));
assign   SRAM_AD[25:20] = rdpcr_en ? pcr_rda[24:19] : (sd_rd_en ? sd_ra[24:19] : sd_wa[24:19]);


//debug
assign pcr_rdatest = pcr_rda[7:4];
//debugend

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
    pcrbuf <= 0;
end
else if(SD_RD_ENA/* && rdpcr_en*/) begin
    if(SD_BURST_LEN[0]) 
        pcrbuf[15:0] <= SRAM_DI;
    else 
        pcrbuf[31:16] <= SRAM_DI;
end


always @(posedge CLKM or negedge ResetN)
begin
   if(!ResetN)
      cur_st <= IDLE;
   else 
      cur_st <= nxt_st;
end

always @(ResetN or cur_st or RxDEN or RxFSYNC or FValid or FirstFr or TFRAME or WR_EN or RD_EN or
         sd_ra or sd_wa or TCNT or RCNT or TxDataReq or Send_0Frame or BLK0VALID or BLK1VALID or
         MAX_SEG or SegTxEn or pcr_st or PAUSE or PLAYEND or TSEG or SD_BURST_LEN or StartEn)
begin
if(!ResetN) begin
   nxt_st <= IDLE;
end
else begin
   case (cur_st)
      IDLE : begin
             if(RxDEN)
                nxt_st <= WRS0;
             else
                nxt_st <= IDLE;
             end
      WRS0 : begin //if to write into sdram, Set token
             if(PLAYEND)
                nxt_st <= SENDPEND0;
             else
                nxt_st <= WRS1;
             end
      WRS1 : begin //write: set sram_wr = 0 , set blktable if need
             nxt_st <= WRS2;
             end
      WRS2 : begin //sram_wr = 0
             nxt_st <= WRS3;
             end
      WRS3 : begin //SET sram_wr = 1
             nxt_st <= WRS4;        
             end
      WRS4 : begin
             nxt_st <= WRS5; // 1
             end
      WRS5 : begin // 1
             if(!PAUSE && TxDataReq)
                 nxt_st <= RDS0;
             else if(RxFSYNC)
                 nxt_st <= REFRESH1;
             else
                 nxt_st <= PCRS0;
             end
      RDS0 : begin //if can read
             if(Send_0Frame) begin
                if(BLK0VALID && BLK1VALID && StartEn/* && no_blk_av*/)
                   nxt_st <= RDS1;
                else
                   nxt_st <= WAIT_DEN;
             end    
             else begin
                if(!RD_EN)
                   nxt_st <= WAIT_DEN;
                else begin
                   if(TFRAME==1 && TCNT==FRAME_CNT) begin
                      if((TSEG+7'h01)>=MAX_SEG)
                         nxt_st <= SENDPEND0;
                      else begin 
                         if(SegTxEn) 
                            nxt_st <= RDS1;
                         else
                            nxt_st <= WAIT_DEN;
                      end
                   end
                   else begin //TFRAME!=1 || TCNT!=8'd188
                      nxt_st <= RDS1;
                   end
                end
             end
             end
      RDS1 : begin // sdram_rd = 0
             nxt_st <= RDS2;
             end     
      RDS2 : begin // 0
             nxt_st <= RDS3;
             end    
      RDS3 : begin // 1
             nxt_st <= RDS4;
             end  
      RDS4 : begin // 1
             if(SD_BURST_LEN[0])
                nxt_st <= WAIT_DEN;
             else
                nxt_st <= RDS4;
             end
      REFRESH1 : begin // sram_fresh = 1
                 nxt_st <= REFRESH2;
                 end
      REFRESH2 : begin // sram_fresh = 0;
                 nxt_st <= REFRESH3;
                 end      
      REFRESH3 : begin // 0
                 nxt_st <= REFRESH4;
                 end
      REFRESH4 : begin // sram_fresh = 1;
                 nxt_st <= WAIT_DEN;
                 end      
      PCRS0 : begin
              if((pcr_st==3'b000) || (pcr_st==3'b111))
                 nxt_st <= WAIT_DEN;
              else if(pcr_st==3'b100)
                 nxt_st <= PCRS5;
              else 
                 nxt_st <= PCRS1;
              end
      PCRS1 : begin //sram_rd = 0
              nxt_st <= PCRS2;
              end
      PCRS2 : begin // 0
              nxt_st <= PCRS3;
              end
      PCRS3 : begin // 1
              if(SD_BURST_LEN[0])
                 nxt_st <= PCRS4;
              else
                 nxt_st <= PCRS3;
              end
      PCRS4 : begin // 1
//              nxt_st <= WAIT_DEN;
              if(RxDEN) 
                 nxt_st <= WRS0;
              else
                 nxt_st <= WAIT_DEN;
              end        
      PCRS5 : begin
              nxt_st <= PCRS6;
              end
      PCRS6 : begin
              nxt_st <= PCRS7;
              end
      PCRS7 : begin
              nxt_st <= PCRS8;
              end
      PCRS8 : begin
//              nxt_st <= WAIT_DEN;
              if(RxDEN) 
                 nxt_st <= WRS0;
              else
                 nxt_st <= WAIT_DEN;
              end
      WAIT_DEN : begin
                 if(RxDEN) 
                     nxt_st <= WRS0;
                 else
                     nxt_st <= WAIT_DEN;
                 end
      SENDPEND0 : begin
                  nxt_st <= SENDPEND1;
                  end
      SENDPEND1 : begin
                  nxt_st <= SENDPEND2;
                  end
      SENDPEND2 : begin
                  nxt_st <= SENDPEND2;
                  end
      default : begin
                nxt_st <= IDLE;
                end
   endcase
end
end
                  
always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
   pcr_st <= 0;
   TxFSYNC <= 0;
   Send_0Frame <= 1;
   Search_0SEG <= 1;
   SPCR0 <= 0;
   SPCR1 <= 0;
   SPCR2 <= 0;
   SetFNUM <= 0;
   SetData <= 0; 
   SRAM_WR <= 1;
   SRAM_RD <= 1;
   SRAM_FRESH <= 1;
   sd_wa <= 0;
   sd_ra <= 0;
   pcr_rda <= 0;
   sd_rd_en <= 0;
   rdpcr_en <= 0;
   BlkIndex <= 0;
   BlkData <= 0;
   BlkValid <= 0;
   BlkStb <= 0;
   TSEG <= 0;
   ReadSEG <= 0;
   LPEND <= 1;
   pcr_fnum <= 0; 
   TFRAME <= 0;
   RCNT <= 0;
   TCNT <= 0;
   WR_EN <= 0;
   RD_EN <= 0;
   PreSegIndex <= 0;
   endframe <= 0;
   ContWR <= 0;
   RdEnd <= 0;
   endferr <= 0;
//   pcrtestbit <= 0;
   pcrerr <= 0;
end else begin
   case (cur_st)
     IDLE : begin
	    pcr_st <= 0;
	    TxFSYNC <= 0;
	    Send_0Frame <= 1;
	    Search_0SEG <= 1;
	    SPCR0 <= 0;
	    SPCR1 <= 0;
	    SPCR2 <= 0;
	    SetFNUM <= 0;
	    SetData <= 0; 
	    SRAM_WR <= 1;
	    SRAM_RD <= 1;
 	    SRAM_FRESH <= 1;