wraddrreg.v

华大机顶盒源码(包括所有源代码).rar

module WrAddrReg( CLKM, ResetN, 
                  //input 
                  IncEn, NxtFrame, SetNewSeg, 
                  NewSegSA, 
                  //output 
                  WrAddr, New , EndAddr
                );
                
input CLKM;
input ResetN;

input IncEn;
input NxtFrame;
input SetNewSeg; 
input [15:0] NewSegSA; 

output [27:0] WrAddr; 
output        New;
output [27:0] EndAddr;

reg [25:0] sd_wa; 
reg        New;
reg [27:0] EndAddr;
reg [5:0]  RCNT; 

assign WrAddr[1:0] = 2'b00; 
assign WrAddr[27:2] = sd_wa;  

parameter FRAME_CNT = 6'd47;

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	sd_wa <= 0;
        New <= 1;
        EndAddr <= 28'hBC;
        RCNT <= 0;
end
else begin
	if(SetNewSeg) begin
		sd_wa <= {NewSegSA,10'b0000_0000_00};
		EndAddr <= {NewSegSA, 12'h0BC};					
		New <= 1;
		RCNT <= 0;
	end
	else if(IncEn) begin
		sd_wa <= sd_wa + 1;
		New <= 0;
		RCNT <= RCNT + 1;
	end
	else if(NxtFrame) begin
		sd_wa <= sd_wa + FRAME_CNT - RCNT;
		EndAddr <= EndAddr + 8'hBC;
		New <= 0;
		RCNT <= 0;
	end
	else begin
		sd_wa <= sd_wa;
		New <= New;
	end
end

endmodule