📄 sdrcnt.v
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//cntr_limit,
burst_length_cntr,
burst_cntr_ena
);
// ****************************************
//
// I/O DEFINITION
//
// ****************************************
// System level stuff
input sys_rst_l;
input sys_clk;
// SDRAM connections
output sd_wr_l;
output sd_cs_l;
output sd_ras_l;
output sd_cas_l;
output sd_dqm;
// Host Controller connections
input do_mode_set;
input do_read;
input do_write;
output doing_refresh;
output [1:0] sd_addx_mux;
//output [1:0] sd_addx10_mux;
output sd_rd_ena;
output sd_data_ena;
input [2:0] modereg_cas_latency;
input [2:0] modereg_burst_length;
output mp_data_mux;
//input decoded_dqm;
output do_write_ack;
output do_read_ack;
output do_modeset_ack;
output pwrup;
output Ref_expired;
output modeset_cyc;
//Add doing refresh signal
input refresh_l;
// Debug
//output [3:0] next_state;
//output [3:0] autorefresh_cntr;
//output autorefresh_cntr_l;
//output [12:0] cntr_limit;
output [3:0] burst_length_cntr;
output burst_cntr_ena;
// ****************************************
//
// Memory Elements
//
// ****************************************
//
//reg [3:0] next_state;
reg [16:0] next_state;
//reg [(`BW-1):0] refresh_timer;
reg sd_wr_l;
reg sd_cs_l;
reg sd_ras_l;
reg sd_cas_l;
reg sd_dqm;
reg [1:0] sd_addx_mux;
//reg [1:0] sd_addx10_mux;
reg sd_data_ena;
reg pwrup; // this variable holds the power up condition
reg [12:0] refresh_cntr; // this is the refresh counter
reg refresh_cntr_l; // this is the refresh counter reset signal
reg [3:0] burst_length_cntr;
reg burst_cntr_ena;
reg sd_rd_ena; // read latch gate, active high
reg [12:0] cntr_limit;
reg [3:0] modereg_burst_count;
reg [2:0] refresh_state;
reg mp_data_mux;
wire do_refresh; // this bit indicates autorefresh is due
reg doing_refresh; // this bit indicates that the state machine is
// doing refresh.
reg [3:0] autorefresh_cntr;
reg autorefresh_cntr_l;
reg do_write_ack;
reg do_read_ack;
reg do_modeset_ack;
reg do_refresh_ack;
reg Ref_expired;
reg modeset_cyc;
wire Trc_expired;
assign Trc_expired = (autorefresh_cntr == 4'h3);
//assign Ref_expired = (refresh_cntr == cntr_limit);
always @( refresh_cntr or cntr_limit )
if (refresh_cntr == cntr_limit)
Ref_expired <= 1'b1;
else
Ref_expired <= 1'b0;
// State Machine
always @(posedge sys_clk or negedge sys_rst_l)
if (~sys_rst_l) begin
next_state <= `state_powerup;
autorefresh_cntr_l <= `LO;
refresh_cntr_l <= `LO;
pwrup <= `HI; // high indicates we've just power'd up or RESET
sd_wr_l <= `HI;
sd_cs_l <= `HI;
sd_ras_l <= `HI;
sd_cas_l <= `HI;
sd_dqm <= `HI;
sd_data_ena <= `LO;
sd_addx_mux <= 2'b10; // select the mode reg default value
//sd_addx10_mux <= 2'b11; // select 1 as default
sd_rd_ena <= `LO;
mp_data_mux <= `LO;
// refresh_cntr<= 13'h0000;
burst_cntr_ena <= `LO; // do not enable the burst counter
doing_refresh <= `LO;
do_write_ack <= `LO; // do not ack as reset default
do_read_ack <= `LO; // do not ack as reset default
do_modeset_ack <= `LO; // do not ack as reset default
do_refresh_ack <= `LO;
end
else case (next_state)
// Power Up state
`state_powerup: begin
next_state <= `state_precharge;
sd_wr_l <= `HI;
sd_cs_l <= `HI;
sd_ras_l <= `HI;
sd_cas_l <= `HI;
sd_dqm <= `HI;
sd_data_ena <= `LO;
sd_addx_mux <= 2'b10;
sd_rd_ena <= `LO;
pwrup <= `HI; // this is the power up run
burst_cntr_ena <= `LO; // do not enable the burst counter
refresh_cntr_l <= `HI; // allow the refresh cycle counter to count
end
// PRECHARGE both (or all) banks
`state_precharge: begin
sd_wr_l <= `LO;
sd_cs_l <= `LO;
sd_ras_l <= `LO;
sd_cas_l <= `HI;
sd_dqm <= `HI;
modeset_cyc <= `HI;
sd_addx_mux <= 2'b11; // A10 = 1'b1
next_state <= `state_idle;
sd_rd_ena <= `LO; // done with the reading
if (do_write_ack)
do_write_ack<= `LO; // done acknowledging the write request
if (do_read_ack)
do_read_ack <= `LO; // done acknowledging the read request
end
// Delay Trp
// this delay is needed to meet the minimum precharge to new command
// delay. For most parts, this is 20nS, which means you need 1 clock cycle
// of NOP at 100MHz
`state_delay_Trp: begin
sd_wr_l <= `HI;
sd_cs_l <= `HI;
sd_ras_l <= `HI;
if ( (refresh_cntr == cntr_limit) & (pwrup == `HI) ) begin
doing_refresh <= `LO; // refresh cycle is done
refresh_cntr_l <= `LO; // ..reset refresh counter
next_state <= `state_modeset; // if this was power-up, then go and set mode reg
end else begin
doing_refresh <= `HI; // indicate that we're doing refresh
next_state <= `state_auto_refresh;
end
end
// Autorefresh
`state_auto_refresh: begin
sd_wr_l <= `HI;
sd_cs_l <= `LO;
sd_ras_l <= `LO;
sd_cas_l <= `LO;
//sd_addx10_mux <= 2'b01; // A10 = 0
next_state <= `state_auto_refresh_dly;
autorefresh_cntr_l <= `HI; //allow refresh delay cntr (Trc) to tick
do_refresh_ack <= `HI; // acknowledge refresh request
end
// This state generates the Trc delay.
// this delay is the delay from the refresh command to the next valid command
// most parts require this to be 60 to 70nS. So at 100MHz, we need at least
// 6 NOPs.
`state_auto_refresh_dly: begin
sd_wr_l <= `HI;
sd_cs_l <= `HI;
sd_ras_l <= `HI;
sd_cas_l <= `HI;
//sd_addx10_mux <= 2'b00; // select ROW again A10 = A20
// Wait for Trc
if (autorefresh_cntr == 4'h3) begin
autorefresh_cntr_l <= `LO; // reset Trc delay counter
// Check if the number of specified back-back refreshes are done
if (refresh_cntr == cntr_limit) begin
doing_refresh <= `LO; // refresh cycle is done
refresh_cntr_l <= `LO; // ..reset refresh counter
// if this is not a power-up sequence, and there are pending
// requests, then service it.
if (~pwrup)
if (do_write | do_read)
next_state <= `state_set_ras; // go service a pending read or write if any
else
next_state <= `state_idle; // if there are no peding RD or WR, then go to idle state
// if this is part of power-up sequencing, we need to go and
// set mode register.
else
next_state <= `state_modeset;
end
// IF refresh cycles not done yet, keep issuing autorefresh commands
else
next_state <= `state_auto_refresh;
end
// If Trc has not expired
else begin
next_state <= `state_auto_refresh_dly;
do_refresh_ack <= `LO;
end
end
// MODE SET state
`state_modeset: begin
next_state <= `state_idle;
sd_wr_l <= `LO;
sd_cs_l <= `LO;
sd_ras_l <= `LO;
sd_cas_l <= `LO;
sd_addx_mux <= 2'b10;
//sd_addx10_mux <= 2'b10;
modeset_cyc <= `HI;
doing_refresh <= `LO; // deassert
if (pwrup)
pwrup <= `LO; // ..no more in power up mode
if (do_mode_set)
do_modeset_ack <= `LO;
end
// IDLE state
`state_idle: begin
sd_wr_l <= `HI;
sd_cs_l <= `HI;
sd_ras_l <= `HI;
sd_cas_l <= `HI;
sd_data_ena <= `LO; // turn off the data bus drivers
mp_data_mux <= `LO; // drive the SD data bus with normal data
sd_addx_mux <= 2'b00; // select ROW (A[19:10]) of mp_addx to SDRAM
modeset_cyc <= `LO;
burst_cntr_ena <= `LO; // do not enable the burst counter
//sd_addx10_mux <= 2'b00; // select ROW (A[20]) " "
// if we've just come out of system reset (or powerup)
// then we need to go and do initialization sequence.
// Or, if a refresh is requested, go and service it.
if (do_refresh | pwrup) begin
doing_refresh <= `HI; // indicate that we're doing refresh
refresh_cntr_l <= `HI; // allow refresh cycle counter to count up
next_state <= `state_auto_refresh;
end
// if a single word rad or write request is pending, go and service it
else if (do_write | do_read )
next_state <= `state_set_ras;
// if a mode register set is requested, go and service it
else if (do_mode_set) begin
do_modeset_ack <= `HI; // acknowledge the mode set request
next_state <= `state_modeset;
doing_refresh <= `HI; // techincally we're not doing refresh, but
end // this signal is used to prevent the do_write be deasserted
// by the mode_set command.
end
/*
// SET RAS state
`state_set_ras: begin
sd_cs_l <= `LO; // enable SDRAM
sd_ras_l <= `LO; // enable the RAS
next_state <= `state_ras_dly; // wait for a bit
end
// RAS delay state.
// This delay is needed to meet Trcd delay. This is the RAS to CAS delay.
// for most parts this is 20nS. So for 100MHz operation, there needs to be
// at least 1 NOP cycle.
`state_ras_dly: begin
sd_cs_l <= `HI; // disable SDRAM
sd_ras_l <= `HI; // disble the RAS
sd_addx_mux <= 2'b01; // select COLUMN
//sd_addx10_mux <= 2'b01; // select COLUMN
if (do_write) begin
sd_data_ena <= `HI; // turn on the data bus drivers
next_state <= `state_write; // if write, do the write
end else begin
// sd_dqm <= {DQM{`LO}};
next_state <= `state_set_cas; // if read, do the read
end
end
*/
// SET RAS state
`state_set_ras: begin
sd_cs_l <= `LO; // enable SDRAM
sd_ras_l <= `LO; // enable the RAS
sd_addx_mux <= 2'b00;
//sd_addx10_mux <= 2'b01; // select COLUMN
if (do_write) begin
sd_data_ena <= `HI; // turn on the data bus drivers
next_state <= `state_write; // if write, do the write
end else begin
// sd_dqm <= {DQM{`LO}};
next_state <= `state_set_cas; // if read, do the read
end
end
// WRITE state
`state_write: begin
sd_addx_mux <= 2'b11; // select COLUMN
sd_ras_l <= `HI; // disble the RAS
sd_cs_l <= `LO; // enable SDRAM
sd_cas_l <= `LO; // enable the CAS
sd_wr_l <= `LO; // enable the write
do_write_ack<= `HI; // acknowledge the write request
sd_dqm <= 1'b0; // masks the data which is meant to be
//next_state <= `state_delay_Tras1;
next_state <= `state_write_c;
burst_cntr_ena <= `HI; // enable the burst counter
end
`state_write_c: begin
sd_addx_mux <= 2'b00;
sd_ras_l <= `HI;
sd_cs_l <= `HI;
sd_wr_l <= `HI;
sd_cas_l <= `HI;
next_state <= `state_delay_Tras1;
end
`state_delay_Tras1: begin
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