sdrcnt.v

华大机顶盒源码(包括所有源代码).rar

`include "inc.h"

module sdrcnt( 
            // SYSTEM LEVEL CONNECTIONS
            sys_rst_l,
            sys_clk,
	    sd_clk,  

	    // Add doing refresh signal
	    refresh_l,

            // SDRAM CONNECTIONS
            sd_wr_l,
            sdram_cs,
            sd_ras_l,
            sd_cas_l,
            sdram_dqm,
            sdram_cke,
            sd_addx,
//            sd_data1, 
//            sd_data2,
            sd_data_in1,
            sd_data_in2,
            sd_data_in3,
            sd_data_in4,
            sd_data_out1, 
            sd_data_out2,
            sd_data_out3, 
            sd_data_out4,
            sd_data_ena,
            sd_ba,
            // MICROPORCESSOR CONNECTION
            mp_addx,
            mp_data_in1,
            mp_data_out1,
            mp_data_in2,
            mp_data_out2,
            mp_rd_l,
            mp_wr_l,
//            sdram_mode_set_l,
//            sdram_busy_l,
	    // HOST CONNECTIONS
	    sram_csa,
	    sd_rd_ena, // test
	    //debug
	    reg_modeset,
	    burst_length_cntr,
            burst_cntr_ena,
            Ref_expired
 );

// include this file for memory definition



// ****************************************
//
//   I/O  DEFINITION
//
// ****************************************
// SYSTEM LEVEL CONNECTIONS
input           sys_rst_l;              // global active low asynchronous system reset
input           sys_clk;                // global system clock.  Runs the sdram state machine
output          sd_clk;

// Add doing refresh signal
input           refresh_l;

// SDRAM CONNECTIONS
output          sd_wr_l;                // SDRAM active low WRITE signal
output  [3:0]   sdram_cs;                // SDRAM active low chip select signal
output          sd_ras_l;               // SDRAM active low RAS 
output          sd_cas_l;               // SDRAM active low CAS
output  [3:0]   sdram_dqm;                 // SDRAM data masks
output  [1:0]   sdram_cke;
output  [11:0]  sd_addx;                // SDRAM multiplexed address bus
//inout   [7:0]   sd_data1;                // SDRAM birectional data bus 32 bit
//inout   [7:0]   sd_data2;                // SDRAM birectional data bus 32 bit
input   [7:0]   sd_data_in1;
input   [7:0]   sd_data_in2;
output  [7:0]   sd_data_out1;
output  [7:0]   sd_data_out2;
input   [7:0]   sd_data_in3;
input   [7:0]   sd_data_in4;
output  [7:0]   sd_data_out3;
output  [7:0]   sd_data_out4;
output          sd_data_ena;
output  [1:0]   sd_ba;                  // SDRAM bank address , aka A11
// MICROPROCESSOR CONNECTION
input   [7:0]   mp_data_in1;             
output  [7:0]   mp_data_out1;
input   [7:0]   mp_data_in2;             
output  [7:0]   mp_data_out2;
input   [23:0]  mp_addx;                // HOST address bus. 21 bits for 2Mb
input           mp_rd_l;                // HOST active low READ 
input           mp_wr_l;                // HOST active low WRITE
//input           sdram_mode_set_l;
//output          sdram_busy_l;
//HOST CONNECTION
input   [2:0]   sram_csa;

reg     [3:0]   sdram_cs;
reg     [1:0]   sdram_cke;
reg     [3:0]   sdram_dqm;

wire    [7:0]   mp_simulator_data;

// DEBUG
output          sd_rd_ena; // test
output  [13:0]  reg_modeset;
output  [3:0]   burst_length_cntr;
output          burst_cntr_ena;
output          Ref_expired;

// INTER-MODULE CONNECTIONS
wire            do_modeset;
wire            do_read;
wire            do_write;
wire            doing_refresh;
wire            sd_addx_ena;
wire    [1:0]   sd_addx_mux;
wire            sd_rd_ena;
wire            sd_data_ena;
wire    [2:0]   modereg_cas_latency;
wire    [2:0]   modereg_burst_length;
wire    [7:0]   mp_data_in1;
wire    [7:0]   mp_data_in2;
wire            mp_wr_l;
wire            mp_rd_l;
wire            mp_data_mux;
wire            pwrup;
wire    [3:0]   top_state;
//wire    [23:0]  reg_mp_addx;
//wire            decoded_dqm;
wire            do_write_ack;
wire            do_read_ack;
wire            do_modeset_ack;
wire    [7:0]   reg_mp_data_mux;
//wire    [7:0]   reg_sd_data1;
//wire    [7:0]   reg_sd_data2;
//wire            sdram_mode_set_l;
//wire            sdram_busy_l;
wire            sd_cs_l;
wire            Ref_expired;
wire            sd_dqm;
wire            modeset_cyc;


//
// SDRAM side bidirectional data bus drivers
//assign sd_data1    = sd_data_ena ? sd_data_out1 : 8'hzz;
//assign sd_data2    = sd_data_ena ? sd_data_out2 : 8'hzz;
//

//assign sd_data_in1 = sd_data1;
//assign sd_data_in2 = sd_data2;

assign  sd_clk = ~sys_clk;
//assign  sd_clk = sys_clk;

//multi SDRAM chip select signal
always @( sram_csa or Ref_expired or sd_cs_l or sd_dqm or modeset_cyc or sys_rst_l)
  if (~sys_rst_l) begin
      sdram_cs[3:0] = 4'b1111;
      sdram_dqm[3:0] = 4'b1111;
      sdram_cke[1:0] = 2'b00;
      end
  else
  case ({modeset_cyc, Ref_expired, sram_csa})
    5'b00000: begin
      sdram_cs[3:0] = 4'b1110; //{2'b11, sd_cs_l,sd_cs_l};
      sdram_dqm[3:0] = {3'b111, sd_dqm};
      sdram_cke[1:0] = 2'b11;
      end
    5'b00001:  begin
      sdram_cs[3:0] = 4'b1011; //{2'b11, sd_cs_l, sd_cs_l};
      sdram_dqm[3:0] = {2'b11, sd_dqm, 1'b1};
      sdram_cke[1:0] = 2'b11;
      end
    5'b00010:  begin
      sdram_cs[3:0] = 4'b1110; //{sd_cs_l, sd_cs_l, 2'b11};
      sdram_dqm[3:0] = {1'b1, sd_dqm, 2'b11};
      sdram_cke[1:0] = 2'b11;
      end
    5'b00011:  begin
      sdram_cs[3:0] = 4'b1011; //{sd_cs_l, sd_cs_l, 2'b11};
      sdram_dqm[3:0] = {sd_dqm, 3'b111};
      sdram_cke[1:0] = 2'b11;
      end
    5'b00100: begin
      sdram_cs[3:0] = 4'b1101; //{2'b11, sd_cs_l,sd_cs_l};
      sdram_dqm[3:0] = {3'b111, sd_dqm};
      sdram_cke[1:0] = 2'b11;
      end
    5'b00101:  begin
      sdram_cs[3:0] = 4'b0111; //{2'b11, sd_cs_l, sd_cs_l};
      sdram_dqm[3:0] = {2'b11, sd_dqm, 1'b1};
      sdram_cke[1:0] = 2'b11;
      end
    5'b00110:  begin
      sdram_cs[3:0] = 4'b1101; //{sd_cs_l, sd_cs_l, 2'b11};
      sdram_dqm[3:0] = {1'b1, sd_dqm, 2'b11};
      sdram_cke[1:0] = 2'b11;
      end
    5'b00111:  begin
      sdram_cs[3:0] = 4'b0111; //{sd_cs_l, sd_cs_l, 2'b11};
      sdram_dqm[3:0] = {sd_dqm, 3'b111};
      sdram_cke[1:0] = 2'b11;
      end      
    default :  begin
      sdram_cs[3:0] = {sd_cs_l, sd_cs_l, sd_cs_l, sd_cs_l};
      sdram_dqm[3:0] = {sd_dqm, sd_dqm, sd_dqm, sd_dqm};
      sdram_cke[1:0] = 2'b11;
      end

  endcase

//
// INSTANTIATE THE SDRAM STATE MACHINE
//
sdramcnt U1(    
                .sys_rst_l(sys_rst_l),
                .sys_clk(sys_clk),
                .sd_wr_l(sd_wr_l),
                .sd_cs_l(sd_cs_l),
                .sd_ras_l(sd_ras_l),
                .sd_cas_l(sd_cas_l),
                .sd_dqm(sd_dqm),
	     		.refresh_l(refresh_l),
		        .Ref_expired(Ref_expired),
                .do_mode_set(1'b0),
                .do_read(do_read),
                .do_write(do_write),
                .doing_refresh(doing_refresh),
                .sd_addx_mux(sd_addx_mux),
                .sd_rd_ena(sd_rd_ena),
                .sd_data_ena(sd_data_ena),
                .modereg_cas_latency(modereg_cas_latency),
                .modereg_burst_length(modereg_burst_length),
                .mp_data_mux(mp_data_mux),
//                .decoded_dqm(decoded_dqm),
                .do_write_ack(do_write_ack),
                .do_read_ack(do_read_ack),
                .do_modeset_ack(do_modeset_ack),
		.modeset_cyc(modeset_cyc),
                .pwrup(pwrup),
                .burst_length_cntr(burst_length_cntr),
                .burst_cntr_ena(burst_cntr_ena)
    );



//
//  INSTANTIATE THE HOST INTERFACE LOGIC
// 
hostcont U2(
            // system connections
                .sys_rst_l(sys_rst_l),            
                .sys_clk(sys_clk),

            // microprocessor side connections
                .mp_addx(mp_addx),
                .mp_data_in1(mp_data_in1),
                .mp_data_in2(mp_data_in2),
                //.mp_data_out(mp_data_out_sd),
                .mp_data_out1(mp_data_out1),
                .mp_data_out2(mp_data_out2),
                .mp_rd_l(mp_rd_l),
                .mp_wr_l(mp_wr_l),
//                .sdram_mode_set_l(sdram_mode_set_l),
//                .sdram_busy_l(sdram_busy_l),

            // SDRAM side connections
                .sd_addx(sd_addx),
                .sd_data_in1(sd_data_in1),
                .sd_data_out1(sd_data_out1),
                .sd_data_in2(sd_data_in2),
                .sd_data_out2(sd_data_out2),
                .sd_data_in3(sd_data_in3),
                .sd_data_out3(sd_data_out3),
                .sd_data_in4(sd_data_in4),
                .sd_data_out4(sd_data_out4),
                .sd_ba(sd_ba),
                
            // SDRAMCNT side
                //.sd_addx10_mux(sd_addx10_mux),
                .sdram_dqm(sdram_dqm),
                .sd_addx_mux(sd_addx_mux),
                .sd_rd_ena(sd_rd_ena),
                .do_read(do_read),
                .do_write(do_write),
//                .doing_refresh(doing_refresh),
//                .do_modeset(do_modeset),
                .modereg_cas_latency(modereg_cas_latency),
                .modereg_burst_length(modereg_burst_length),
                .mp_data_mux(mp_data_mux),
//                .decoded_dqm(decoded_dqm),
//                .do_write_ack(do_write_ack),
//                .do_read_ack(do_read_ack),
//                .do_modeset_ack(do_modeset_ack),
                .pwrup(pwrup),

            // debug
                //.reg_mp_data_mux(reg_mp_data_mux),
                //.reg_mp_addx(reg_mp_addx),
                //.reg_sd_data(reg_sd_data)
                .reg_modeset(reg_modeset)

             );


endmodule

/*******************************************************************************/
/*******************************************************************************/

//`include "inc.h"

module sdramcnt(	
		// system level stuff
		sys_rst_l,
		sys_clk,
		
		// SDRAM connections
		sd_wr_l,
		sd_cs_l,
		sd_ras_l,
		sd_cas_l,
		sd_dqm,
			
		// Host Controller connections
	    	do_mode_set,
	  	do_read,
                do_write,
                doing_refresh,
                sd_addx_mux,
                //sd_addx10_mux,
                sd_rd_ena,
                sd_data_ena,
                modereg_cas_latency,
                modereg_burst_length,
                mp_data_mux,
//	        decoded_dqm,
                do_write_ack,
                do_read_ack,
                do_modeset_ack,
		// Add doing refresh signal
		refresh_l,
		Ref_expired,

		//in mode set cycle
		modeset_cyc,

                pwrup,

		// debug
                //next_state,
	        //autorefresh_cntr,
	        //autorefresh_cntr_l,