irmodule.v

华大机顶盒源码(包括所有源代码).rar

module IRmodule(ResetN, CLKM, SendEn, ir, ir_en, Start);

input ResetN;
input CLKM;
input SendEn;

output ir;
output ir_en;
output Start;

reg    ir ;
reg    ir_en;
reg    Start;

reg [11:0]  clkcnt;
reg         clk6k25;
reg [4:0]   i;
reg [5:0]   st_cnt;
reg [2:0]   cur_st;

parameter idle = 3'b000, send_head0 = 3'b001, send_head1 = 3'b010, send_head2 = 3'b011,
          send_head3 = 3'b100, send_bit_st1= 3'b101, send_bit_st2 = 3'b110, send_nxt_bit = 3'b111;          

parameter StartDW = 32'h20DFB847,
          StopDW  = 32'h20DF926D;

wire [31:0] SendDW = Start ? StopDW : StartDW;
wire [5:0]  OneWidth = SendDW[i] ? 6'h09 : 6'h02; 

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
   clkcnt <= 0;
   clk6k25 <= 0;
end else if(clkcnt == 12'hC7F) begin
   clkcnt <= 0;
   clk6k25 <= 1;
end else begin
   clkcnt <= clkcnt + 1;
   clk6k25 <= 0;
end

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
   ir <= 1;
   ir_en <= 0;
   Start <= 0;      
   cur_st <= 0;
   st_cnt <= 0;
   i <= 5'b11111;
end
else begin     
   case (cur_st)
     idle : begin
            if(SendEn)
              cur_st <= send_head0;
            ir <= 1;
            ir_en <= 0;
            Start <= Start;
            st_cnt <= 0;
            i <= 5'b11111;
            end
     send_head0 : begin
                  if(clk6k25)            
                     cur_st <= send_head1;
                  else
                     cur_st <= send_head0;
                  st_cnt <= 0;
                  ir <= 1;
                  ir_en <= 1;
                  Start <= Start;            
                  i <= i;
                  end            
     send_head1 : begin
                  if(clk6k25 && st_cnt==6'h38)
                     cur_st <= send_head2;
                  else
                     cur_st <= send_head1;
                  if(clk6k25) begin
                     if(st_cnt==6'h38)
                        st_cnt <= 0;
                     else
                        st_cnt <= st_cnt + 1;
                  end else st_cnt <= st_cnt;
                  ir <= 0;
                  Start <= Start;
                  i <= i;
                  end           
     send_head2 : begin
                  if(clk6k25 && st_cnt==6'h1B)
                      cur_st <= send_head3;
                  else
                      cur_st <= send_head2;               
                  if(clk6k25) begin
                     if(st_cnt==6'h1B)
                        st_cnt <= 0;
                     else
                        st_cnt <= st_cnt + 1;
                  end else st_cnt <= st_cnt;
                  ir <= 1;
                  end
     send_head3 : begin
                  if(clk6k25 && st_cnt==6'h3)
                     cur_st <= send_bit_st1;
                  else
                     cur_st <= send_head3;               
                  if(clk6k25) begin
                     if(st_cnt==6'h3)
                        st_cnt <= 0;
                     else
                        st_cnt <= st_cnt + 1;
                  end else st_cnt <= st_cnt;
                  ir <= 0;
                  end            
     send_bit_st1 : begin
                  if(clk6k25 && st_cnt==OneWidth)
                     cur_st <= send_bit_st2;
                  else 
                     cur_st <= send_bit_st1;
                  if(clk6k25) begin
                     if(st_cnt==OneWidth)
                       st_cnt <= 0;
                     else
                       st_cnt <= st_cnt + 1;
                  end
                  else 
                     st_cnt <= st_cnt;
                  ir <= 1;
                  end
     send_bit_st2 : begin
                  if(clk6k25 && st_cnt==6'h3)
                     cur_st <= send_nxt_bit;
                  else 
                     cur_st <= send_bit_st2;
                  if(clk6k25) begin
                     if(st_cnt==3'h3)
                       st_cnt <= 0;
                     else
                       st_cnt <= st_cnt + 1;
                  end
                  else 
                     st_cnt <= st_cnt;
                  ir <= 0;
                  end   
     
     send_nxt_bit : begin
                    ir <= ir;
                    if(i==0)
                       Start <= ~Start;
                    else
                       Start <= Start;
                    if(i==0)
                       cur_st <= idle;
                    else
                       cur_st <= send_bit_st1;
                    if(i==0)
                       i <= 5'b11111;
                    else
                       i <= i - 1;
                    end
   endcase
end

endmodule