initsegregtab.v

华大机顶盒源码(包括所有源代码).rar

module InitSegRegTab( CLKM, ResetN, 
                      //input 
                      Init_Mem, Req_Mem, Mem_Blk_Num, Mem_Blk_Size, Mem_Sel, 
                      //output 
                      Init_Mem_End, Mem_Fail,
                      RT_DB, RT_WR, RT_WADDR, init_oper 
                      );

input        CLKM;
input        ResetN;

input        Init_Mem;
input [1:0]  Mem_Sel;
input [7:0]  Req_Mem;
input [7:0]  Mem_Blk_Num;
input [15:0] Mem_Blk_Size;

output       Init_Mem_End;
output       Mem_Fail;
output [7:0] RT_DB;
output       RT_WR;
output [9:0] RT_WADDR;
output       init_oper;

reg          Init_Mem_End;
reg          Mem_Fail;
reg    [7:0] RT_DB;
reg          RT_WR;
reg    [9:0] RT_WADDR;
reg          init_oper;
reg   [15:0] SegStartAddr;


reg [9:0] CurState;

parameter Idle = 10'b0000000001,
          CompMemReq = 10'b0000000010,
	  WrSegNum = 10'b0000000100,
	  WrSegNum1 = 10'b0000001000,
	  WrSegNum2 = 10'b0000010000,
	  WrSA1 = 10'b0000100000,
	  WrSA2 = 10'b0001000000,
	  WrSA3 = 10'b0010000000,
	  WrSA4 = 10'b0100000000,
	  InitNxtSeg = 10'b1000000000;

always @(posedge CLKM or negedge ResetN)
if(!ResetN) begin
	Init_Mem_End <= 0;
	Mem_Fail <= 0;
	RT_DB <= 0;
	RT_WR <= 0;
	RT_WADDR <= 0;
	init_oper <= 0;
	SegStartAddr <= 0;
	CurState <= Idle;
end
else begin
	case (CurState)
		Idle :
		begin
			Init_Mem_End <= Init_Mem_End;
			Mem_Fail <= Mem_Fail;
			RT_DB <= 0;
			RT_WR <= 0;
			RT_WADDR <= 0;
			init_oper <= 0;
			SegStartAddr <= 0;
			if(Init_Mem && !Init_Mem_End)	
				CurState <= CompMemReq ;
		end
		CompMemReq :
		begin
			RT_DB <= 8'hFE;
			case (Mem_Sel)
				2'b00 :
				begin
					if(Req_Mem <= 8'h20) begin
		 				init_oper <= 1;
						CurState <= WrSegNum;	
					end
					else begin 
						Mem_Fail <= 1;
						CurState <= Idle;
					end
				end
				2'b01 :
				begin
					if(Req_Mem <= 8'h40) begin
		 				init_oper <= 1;
						CurState <= WrSegNum;	
					end
					else begin 
						Mem_Fail <= 1;
						CurState <= Idle;
					end
				end
				2'b10 : 
				begin
					if(Req_Mem <= 8'h80) begin
		 				init_oper <= 1;
						CurState <= WrSegNum;	
					end
					else begin 
						Mem_Fail <= 1;
						CurState <= Idle;
					end
				end		
				2'b11 : 
				begin
	 				init_oper <= 1;
					CurState <= WrSegNum;	
				end
			endcase
		end
		WrSegNum :
		begin
			RT_WR <= 1;
			if(RT_WADDR[9:3] < Mem_Blk_Num)		
				CurState <= WrSegNum1;
			else
				CurState <= InitNxtSeg;
		end
                WrSegNum1 :
		begin
			RT_WR <= 0;
			RT_WADDR[2:0] <= 3'b001;			
			RT_DB <= 0;
			CurState <= WrSegNum2;
		end	
                WrSegNum2 :
		begin
			RT_WR <= 1;
			CurState <= WrSA1;
		end	
		WrSA1 :
		begin
			RT_WR <= 0;
			RT_WADDR[2:0] <= 3'b010;
			RT_DB <= SegStartAddr[7:0];
			CurState <= WrSA2;
		end
		WrSA2 :
		begin
			RT_WR <= 1;
			CurState <= WrSA3;
		end
		WrSA3 :
		begin
			RT_WR <= 0;
			RT_WADDR[2:0] <= 3'b011;
			RT_DB <= SegStartAddr[15:8];
			CurState <= WrSA4;
		end
		WrSA4 :
		begin
			RT_WR <= 1;
			CurState <= InitNxtSeg;
		end
		InitNxtSeg :
		begin
			RT_WR <= 0;
			RT_WADDR[9:3] <= RT_WADDR[9:3] + 1;
			RT_WADDR[2:0] <= 3'b000;
			SegStartAddr <= SegStartAddr + Mem_Blk_Size;
			if(RT_WADDR[9:3] < (Mem_Blk_Num-1))
				RT_DB <= 8'hFE;
			else
				RT_DB <= 8'hFF;
			if(RT_WADDR[9:3]==7'h7F) begin
				Init_Mem_End <= 1;
				init_oper <= 0;
				CurState <= Idle;
			end
			else begin
				CurState <= WrSegNum;
			end
		end
		default :
		begin
			Mem_Fail <= 1;
			CurState <= Idle;
		end			
		
	endcase
end

                      
endmodule