addrreg.v

来自「华大机顶盒源码(包括所有源代码).rar」· Verilog 代码 · 共 36 行

module AddrReg(ResetN, CLKM, RdIndex, WrIndex, TxIndex, Mem_Sel,
               RdAddr, WrAddr, TxAddr);

input ResetN;
input CLKM;

input [4:0] RdIndex;
input [4:0] WrIndex;
input [4:0] TxIndex; 
input [1:0] Mem_Sel;

output [24:0] RdAddr;
output [24:0] WrAddr;
output [24:0] TxAddr;

reg [20:0] IER1;

assign RdAddr = IER1 * RdIndex;
assign WrAddr = IER1 * WrIndex;
assign TxAddr = IER1 * TxIndex;

always @(Mem_Sel)
begin
  case (Mem_Sel)
//  2'b00 : IER1 <= 27'h249249;
  2'b01 : IER1 <= 21'h124924;
//  2'b10 : IER1 <= 27'h924924;
//  2'b11 : IER1 <= 27'h1249249;
  default : IER1 <= 0;
  endcase
end

endmodule