ctlreg.v

来自「华大机顶盒源码(包括所有源代码).rar」· Verilog 代码 · 共 33 行

module CtrlReg(ResetN, CLKM, 
               //input 
               I2CDB, CEN, WR, MEM_FAIL, PROG_END,
               //output 
               K);
               
input       ResetN;
input       CLKM;
input       CEN;
input       WR;
input       MEM_FAIL;
input       PROG_END;
input [7:0] I2CDB;

output       K;

reg [7:0] CtrReg;

assign K = CtrReg[3];

always @(posedge CLKM or negedge ResetN)
if(!ResetN)
   CtrReg <= 8'h08;
else if(MEM_FAIL || PROG_END)
   CtrReg <= 8'h08;
else if(CEN & WR)
   CtrReg <= I2CDB;
else
   CtrReg <= CtrReg;

endmodule